Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-02-07
2002-09-03
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S070000, C326S081000
Reexamination Certificate
active
06445210
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a level shifter for translating logic levels, and more particularly relates to a level shifter that can substantially eliminate a short-circuit current, which usually flows when a signal changes its logic levels.
A latch-type level shifter is one of known level shifters.
FIG. 32
illustrates a specific configuration for a level shifter of this type. As shown in
FIG. 32
, the level shifter includes two n-channel transistors
51
and
52
, two cross-coupled p-channel transistors
53
and
54
and first and second inverters
55
and
56
. Each of the p-channel transistors
53
or
54
has its gate connected to the drain of the other p-channel transistor
54
or
53
. The first inverter
55
inverts the level of an input signal received at an input terminal IN and is powered by a voltage supply VDD supplying a relatively low voltage of 1.5 V, for example. All the components of the level shifter but the first inverter
55
are powered by another voltage supply VDD
3
supplying a relatively high voltage of 3.3 V, for example. The n-channel transistors
51
and
52
are both grounded and receive signals with mutually complementary levels, i.e., the input signal at the input terminal IN and the output signal of the first inverter
55
, i.e., the inverted version of the input signal, respectively. The p-channel transistors
53
and
54
have their sources connected to the high voltage supply VDD
3
and their drains connected to the drains of the n-channel transistors
51
and
52
, respectively. The second inverter
56
is connected to a second node W
2
at which the n- and the p-channel transistors
52
and
54
are connected together. And the output of the second inverter
56
is connected to an output terminal OUT.
Hereinafter, it will be described how this level shifter operates. Suppose, in a static state, the input signal is at logical 1 level (i.e., equivalent to the level of the supply voltage VDD) and the inverted version thereof is at logical 0 level (i.e., equivalent to the level of the ground potential VSS, or 0 V). In the following description, the logical 1 and 0 levels will be called H- and L-levels, respectively. In such a state, the n- and p-channel transistors
51
and
54
are ON, while the n- and p-channel transistors
52
and
53
are OFF. Also, in this state, a first node W
1
, at which the n- and p-channel transistors
51
and
53
are connected together, is at the L-(VSS) level. On the other hand, the second node W
2
, at which the n- and p-channel transistors
52
and
54
are connected together, is at the H-(VDD
3
) level. Each pair of transistors
51
and
53
or
52
and
54
meets a complementary relationship. Accordingly, no current flows in this static state.
Thereafter, when the level shifter enters an operating state with the transition of the input signal to the L-(VSS) level, the n-channel transistors
51
and
52
turn OFF and ON, respectively, as shown in FIG.
33
. As a result, a short-circuit current I flows from the high voltage supply VDD
3
through the p- and n-channel transistors
54
and
52
in the ON state, and the potential level at the second node W
2
starts to fall from the H-(VDD
3
) level. And when the potential level at the second node W
2
becomes lower than the threshold voltage Vtp of the p-channel transistor
53
, the p-channel transistor
53
turns ON. As a result, the potential level at the first node W
1
rises, the drain current of the p-channel transistor
54
decreases and the potential level at the second node W
2
further falls.
Finally, the potential levels at the first and second nodes W
1
and W
2
reach the H- and L-levels (i.e., VDD
3
level and 0 V), respectively. Then, no short-circuit current flows anymore and the second inverter
56
inverts the output logic level. As a result, the level shifter enters a standby state, or prepares for the next level transition of the input signal. In the foregoing example, the input signal changes from the H- into the L-level. However, a similar statement is applicable to the opposite situation, i.e., where the input signal changes from the L- into the H-level.
In the known level shifter, however, the potential level at the second node W
2
is changed by allowing the short-circuit current to flow through the p- and n-channel transistors
54
and
52
during its operation. Thus, the level shifter dissipates a greater power disadvantageously.
In view of this drawback, a level shifter for selectively interrupting the short-circuit current in accordance with the potential level transition at the output node W
2
was proposed in Japanese Laid-Open Publication Nos. 10-190438 and 7-106946, for example.
FIG. 34
illustrates a configuration for the level shifter of that type. As shown in
FIG. 34
, the level shifter includes not only all the components of the level shifter shown in
FIG. 32
but also p-channel transistors
57
and
58
as current interrupting transistors, which are disposed between the high voltage supply VDD
3
and the p-channel transistors
53
and
54
, respectively. The level shifter further includes inverters
59
,
60
,
61
and
62
as delay devices and a latch
63
of a small size. A potential at the first node W
1
is applied to the gate of one current interrupting transistor
57
by way of the inverters
59
and
60
. A potential at the second node W
2
is applied to the gate of the other current interrupting transistor
58
by way of the inverters
61
and
62
. The latch
63
is connected between the first and second nodes W
1
and W
2
and includes two p-channel transistors
64
and
65
. These transistors
64
and
65
have their sources connected to the high voltage supply and their drains connected to the first and second nodes W
1
and W
2
, respectively. Also, each of these transistors
64
or
65
has its drain connected to the gate of the other transistor
65
or
64
.
In this level shifter with the capability of interrupting the short-circuit current, while the input signal is at the H-level, for example, the potential level at the second node W
2
is also at the H-(VDD
3
) level. In such a state, the current interrupting transistor
58
is OFF and the high voltage supply VDD
3
is disconnected from the p-channel transistor
54
. On the other hand, the potential level at the first node W
1
is at the L-level (i.e., 0 V). In such a state, the p-channel transistor
53
and current interrupting transistor
57
are ON and the high voltage supply VDD
3
is connected to the p-channel transistor
53
.
When the input signal changes into the L-level, the level shifter enters an operating state. In that state, the n-channel transistor
51
turns OFF to disconnect the first node W
1
from the ground. On the other hand, the n-channel transistor
52
turns ON to ground the second node W
2
. As a result, the potential level at the second node W
2
falls. This potential drop is transmitted to the p-channel transistor
58
but its arrival is delayed for a predetermined amount of time by the two delay devices
61
and
62
. During this delay, the potential drop at the second node W
2
turns the p-channel transistor
53
ON to connect the high voltage supply VDD
3
to the first node W
1
. As a result, the potential level at the first node W
1
rises and the p-channel transistor
54
turns OFF. Thereafter, the current interrupting transistor
58
turns ON. Accordingly, even if the n-channel transistor
52
turns ON during this operation, no short-circuit current flows from the high voltage supply VDD
3
through the p- and n-channel transistors
54
and
52
. As a result, the power dissipation can be cut down. However, if the potential rise at the first node W
1
turns the current interrupting transistor
57
OFF after the predetermined time delay, then the first node W
1
might enter a high impedance state and the output might be indefinite. To avoid such an unwanted situation, the latch
63
turns its internal p-channel transistor
64
ON responsive to the potential drop at the second node W
2
.
Le Don Phu
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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