Level shift delay equalization circuit and methodology

Details Level shift delay equalization circuit and methodology Level shift delay equalization circuit and methodology

2005-12-23

2009-06-09

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S063000, C327S333000

Reexamination Certificate

active

07545173

ABSTRACT:
Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input signal from a high state to a low state, the third signal is selected for controlling the output until the first signal attains a high state. The first signal is selected for controlling the output when it has reached a high state after the input signal transition. The first signal remains selected upon transition of the input signal from a high state to a low state. Thus, output delays are equalized and reduced to the shortest delay.

REFERENCES:
patent: 5572156 (1996-11-01), Diazzi et al.
patent: 5933034 (1999-08-01), Hastings et al.
patent: 6351173 (2002-02-01), Ovens et al.
patent: 6717453 (2004-04-01), Aoki

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