Level shift circuit

Details Level shift circuit Level shift circuit

2000-06-09

2002-04-16

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000

Reexamination Certificate

active

06373285

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a level shift circuit.
In the prior art mixed analog-and-digital LSI, a digital block unit X and an analog block unit Y share a power source
66
as shown in FIG.
4
. In general, in such a mixed analog-and-digital LSI, the digital block unit whose voltage can be easily lowered derives power having a lower voltage than in the analog block unit Y so as to reduce power consumption in the digital block unit X, thereby to realize low power consumption.
As shown in
FIG. 5
, in the mixed analog-and-digital LSI which realizes low power consumption with the above structure generally includes a level shift circuit Z which level-shifts a signal received from the digital block unit (digital circuit) X into a high-voltage signal, and enters the level-shifted signal into the analog block unit (analog circuit) Y which has a different power supply voltage from the digital block unit X.
FIG. 3
is a circuit diagram showing the structure of the prior art level shift circuit Z used in the above-mentioned mixed analog-and-digital LSI.
The structure and behavior of the level shift circuit Z which is composed of CMOS transistors will be described as follows based on FIG.
3
. The level shift circuit Z consists of an input unit
41
which operates from a ground potential Vss and a first power source
65
, and an output unit
42
which operates from the ground potential Vss and a second power source
66
.
The input unit
41
has a first CMOS inverter circuit
45
and a second CMOS inverter circuit
48
. The first CMOS inverter circuit
45
has a PMOS transistor
43
and a NMOS transistor
44
arranged in series between the ground potential Vss and the first power source
65
, and their gates and drains are connected, respectively. Similarly, the second CMOS inverter circuit
48
has a PMOS transistor
46
and a NMOS transistor
47
arranged in series between the ground potential Vss and the first power source
65
, and their gates and drains are connected to each other. The first inverter circuit
45
has an input terminal
49
at which a digital signal is entered from the digital block unit X. The digital signal changes its value between the ground potential Vss and the power supply voltage of the first power source
65
. The first inverter circuit
45
has an output terminal
50
connected to the input terminal
51
of the second inverter circuit
48
.
The output unit
42
operates from the ground potential Vss and the second power source
66
. Between the ground potential Vss and the second power source
66
, there are PMOS transistors
53
,
54
whose sources are connected to the second power source
66
, and NMOS transistors
55
,
56
whose sources are connected to the ground potential Vss. A third CMOS inverter circuit
61
is further arranged between the ground potential Vss and the second power source
66
. The third CMOS inverter circuit
61
is composed of a PMOS transistor
59
and a NMOS transistor
60
whose respective gates and drains are connected to each other. The PMOS transistor
53
and the NMOS transistor
55
share a drain
57
, and the PMOS transistor
54
and the NMOS transistor
56
share a drain
58
. The gate of the PMOS transistor
53
is connected to the drain
58
of the PMOS transistor
54
and the NMOS transistor
56
, and the gate of the NMOS transistor
55
is connected to the output terminal
52
of the second inverter circuit
48
in the input unit
41
. The gate of the PMOS transistor
54
is connected to the drain
57
of the PMOS transistor
53
and the NMOS transistor
55
, and the gate of the NMOS transistor
56
is connected to the output terminal
50
of the first inverter circuit
45
. The drain
57
of the PMOS transistor
53
and the NMOS transistor
55
is also connected to the input terminal of the third inverter circuit
61
. The third inverter circuit
61
has an output terminal
62
, which becomes the output of the output unit
42
, and further becomes the level-shifted output of the level shift circuit z.
The behavior of the level shift circuit Z shown in
FIG. 3
will be described as follows.
When the input unit
41
is supplied with the ground potential Vss and the first power source
65
, and the output unit
42
is supplied with the ground potential Vss and the second power source
66
, a first input signal, which sets the ground potential Vss low, and the potential of the first power source
65
high, is entered at the input terminal
49
of the first CMOS inverter circuit
45
.
First, the case where the first input signal makes a LOW to HIGH transition will be described. The output terminal
50
of the first CMOS inverter circuit
45
changes from a HIGH on the first power source
65
to a LOW on the ground potential. The input terminal
51
of the second CMOS inverter circuit
48
is connected to the output terminal
50
of the first CMOS inverter circuit
45
, so the output terminal
52
of the second CMOS inverter circuit
48
changes from a LOW on the ground potential to a HIGH on the first power source
65
. As a result, in the output unit
42
, the NMOS transistor
56
whose gate is connected to the output terminal
50
of the first CMOS inverter circuit
45
is turned off, and the NMOS transistor
55
whose gate is connected to the output terminal
52
of the second CMOS inverter circuit
48
is turned on.
At this moment, the gate of the PMOS transistor
54
goes low, and the PMOS transistor
54
is turned on because the gate of the PMOS transistor
54
is connected to the drain of the NMOS transistor
55
. This makes the drain
58
of the PMOS transistor
54
change to a HIGH on the second power source
66
.
The gate of the PMOS transistor
53
, which is connected to the drain
58
of the PMOS transistor
54
, changes to a HIGH on the second power source
66
, and the PMOS transistor
53
is turned off. As a result of thus turning the PMOS transistor
53
off and the NMOS transistor
55
on, the drain
57
shared by these transistors goes low.
The input of the inverter circuit
61
operating from the second power source
66
is connected to the drain
57
shared by the two MOS transistors
53
and
55
, so the output terminal
62
changes to a HIGH on the second power source
66
.
The following is a description of the case where the first input signal makes a HIGH to LOW transition. The output terminal
50
of the first CMOS inverter circuit
45
changes from a LOW on the first power source
65
to a high, and the output terminal
52
of the second CMOS inverter circuit
48
changes from a HIGH on the first power source
65
to a LOW on the ground potential because the input terminal
51
of the second CMOS inverter circuit
48
is connected to the output terminal
50
of the first CMOS inverter circuit
45
. As a result, in the output unit
42
, the NMOS transistor
56
whose gate is connected to the output terminal
50
of the first CMOS inverter circuit
45
is turned on, and the NMOS transistor
55
whose gate is connected to the output terminal
52
of the second CMOS inverter circuit
48
is turned off.
At this moment, the gate of the PMOS transistor
54
, which is connected to the drain
57
of the NMOS transistor
55
, goes high, and the PMOS transistor
54
is turned off. As a result, the drain
58
of the PMOS transistor
54
changes to a LOW on the ground potential.
The gate of the PMOS transistor
53
, which is connected to the drain
58
of the PMOS transistor
54
, changes its potential to a LOW on the ground potential, and the PMOS transistor
53
is turned on. By thus turning the PMOS transistor
53
on and the NMOS transistor
55
off, the drain
57
shared by these transistors changes to a HIGH on the power supply voltage of the second power source
66
. Since the input of the inverter circuit
61
operating from the second power source
66
is connected to the shared drain
57
, the potential of the output terminal
62
of the output unit
42
changes to a LOW on the ground potential.
As described hereinbefore, the level shift circuit Z shown in
FIG. 3

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