Level sensitive scan design (LSSD) system

Details Level sensitive scan design (LSSD) system Level sensitive scan design (LSSD) system

1979-08-13

1981-10-06

Malzahn, David H.

Boots, shoes, and leggings

307221R, G06F 748, G06F 1100, H03K 2330

Patent

active

042939194

ABSTRACT:
One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a "master" latch and another a "slave". The structure in the patent requires the "master" and "slave" latches to be part of the shift register for scan-in/scan-out. However, only the "master" may be set with data from the logic system surrounding it while the "slave" may only be set with data which previously resided in the related "master" latch. Thus, in those logic organizations where only the "master" latch output is required, the usefulness of the "slave" latch is limited to scan-in/scan-out. In the shift register latch of the invention, the "slave" latch must be set with the data that resided in the related "master" latch during scan-in/scan-out. However, in logic systems requiring the use of only one latch of the shift register latch, both "master" and "slave" latches can perform independent of the other; that is, each latch may be set with data from the logic system without any influence from the other latch in the same shift register latch. Similarly, both "master" and "slave" may feed different sections of the logic surrounding it.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3784907 (1974-01-01), Eichelberger
patent: 3806891 (1974-04-01), Eichelberger et al.
patent: 4063080 (1977-12-01), Eichelberger et al.
patent: 4074851 (1978-02-01), Eichelberger et al.
Bottorff et al., "Test Generation for Large Logic Networks", 14th Design Auto. Conf. Proceedings, Jun. 20-22, 1977, pp. 479-485.
Hsieh et al., "Delay Test Generation", 14th Design Auto. Conf. Proceeding, Jun. 20-22, 1977, pp. 486-491.
Storey et al., "Delay Test Simulation", 14th Design Auto. Conf. Proceedings, Jun. 20-22, 1977, pp. 492-494.
Correia et al., "Introduction to an LSI Test System", 14th Design Automation Conference Proceedings, Jun. 20-22, 1977, New Orleans, Louisiana, pp. 460-461.
Eichelberger et al., "A Logic Design Structure for LSI Testability", 14th Design Auto. Conf. Proceedings, Jun. 20-22, 1977, pp. 462-468.
Godoy et al., "Automatic Checking of Logic Design Structures for Compliance with Testability Ground Rules", 14th Design Auto. Conf. Proceedings, Jun. 20-22, 1977, pp. 469-478.

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