Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2000-05-22
2001-12-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S066000, C326S063000
Reexamination Certificate
active
06333642
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level converting method and a level converting circuit and, more particularly, to the level converting method and circuit suitable for converting an output level of a CMOS (Complementary Metal Oxide Semiconductor) logic circuit to an input level of an ECL (Emitter-Coupled Logic) logic circuit.
2. Description of the Related Art
Such a signal transmission system has been so far known that supplies a CMOS logic circuit's output level via a transmission line to an ECL logic circuit. Since the CMOS logic circuit and the ECL logic circuit have mutually different signal levels (hereinafter referred to as logic levels) of their own, to supply a signal output from the CMOS logic circuit via the transmission line to the ECL logic circuit in order to permit that ECL logic circuit to operate predetermined logic operations, it is necessary to convert the logic level of the signal output from the CMOS logic circuit to the logic level of the ECL logic circuit and then supply thus obtained signal to that ECL logic circuit.
In a prior-art example shown in
FIG. 4
, a CMOS logic circuit
12
which outputs a logic signal to be level-shifted is connected somewhere between a positive power supply V
DD
(typically 5.0V or 3.3V) and a ground potential, to perform full-swing operations between the V
DD
and the ground potential when the logic signal is applied to its input. Then, an ECL logic circuit
26
which receives thus level-shifted logic signal is connected somewhere between the ground potential and a negative power supply V
EE
(typically −5.2V or −4.5V), so that in such a state where a DC (Direct Current) bypass set as a value adapted to perform a logic decision on an input logic signal is applied to its input terminal, it performs logic operations based on the input logic signal at a logic level between the ground potential and the negative power supply V
EE
.
To level-shift the logic level of the logic signal supplied to the ECL logic circuit
26
via a transmission line
22
from the CMOS logic circuit
12
to the logic level of the ECL logic circuit
26
and then apply it to the input of the ECL logic circuit, an input terminal
51
of a source-follower circuit
50
(consisting of an N-channel MOS transistor M
50
) is connected to an output of the CMOS logic circuit and an output terminal
53
of the source-follower
50
is connected to a sending end of the transmission line
22
. A terminating resistor
24
has its one end connected to a receiving end of the transmission line
22
and its other end connected with a negative power supply V
TT
(typically −2V), so that at both of these ends is generated a DC-logic level (PECL level) with a logic amplitude of 800 milli-volts. This DC-logic level is AC-connected via a capacitor
25
to the input of the CMOS logic circuit
12
, thus establishing an interface of the signal level between the CMOS logic circuit
12
performing logic operations on the positive power supply V
DD
and the ECL logic circuit
26
performing logic operations on the negative power supply; that is, the logic level of a logic signal output from the CMOS logic circuit
12
is level-shifted to a logic level matched to the logic operations of the ECL logic circuit
26
.
In contrast to the first prior-art example for transmitting a signal in an AC manner, a second prior-art example shown in
FIG. 5
transmits a logic signal to the ECL logic circuit
26
in a DC manner. That is, it is a level-shifting circuit
60
which is interposed, in configuration, between the CMOS logic circuit
12
and the ECL logic circuit
26
having the same configurations as those in the first example, so as to transmit the logic signal having an interfaced signal level to the input of the ECL logic circuit in the DC manner. Note here that this example assumes that the positive power Supply V
DD
is of 3V and the negative power supply is of −4.5V.
This level shifting circuit
60
includes an open-drain circuit
62
, the transmission line
22
which has its sending end connected with an output terminal
63
of the open-drain circuit
62
, and resistors R
61
and R
62
for Thevein-terminating, in configuration, the transmission line
22
between the ground potential at which the transmission line
22
is terminated and the negative power supply V
TT
(−2V). Thevenin termination here means that a combined resistance of the resistors R
61
and R
62
is made equal to a characteristic impedance value of the transmission line
22
. The terminating end of the level shifting circuit
60
is directly connected to the input of the ECL logic circuit
26
. Also, the open-drain circuit
62
consists essentially of an N-channel MOS transistor M
62
which has its gate electrode connected with an input terminal
61
connected to the output of the CMOS logic circuit
12
and also its source electrode connected with the negative power supply V
TT
.
Thus, by Thevenin-terminating the transmission line
22
connected to the output of the open-drain circuit
62
between the ground potential and the negative power supply V
TT
using the resistors R
61
and R
62
, to connect its terminating end directly to the input of the ECL logic circuit
26
, thus enabling transmitting a signal to the above-mentioned ECL logic circuit
26
in the DC manner.
A third prior-art example shown in
FIG. 6
, like the second prior-art example, performs DC-wise transmission to the ECL logic circuit
26
. That is, this example is a level shifting circuit which his disposed between the CMOS logic circuit
12
and the ECL logic circuit
26
having almost the same configuration as the first prior-art example, in such a configuration that the logic signal with the interfaced signal level may be transmitted to the input of the ECL logic circuit
26
in the DC manner. Note here that this example assumes that the positive power supply V
DD
is of 5V and the negative power supply, of −4.5V. This level shifting circuit
70
includes an N-channel MOS type inverter
72
which has its input terminal
71
connected with the output terminal of the CMOS logic circuit
12
, a clamp circuit
74
connected to the output terminal of the N-channel MOS type inverter
72
, a level shifting circuit
76
connected to the output terminal of the N-channel MOS type inverter
72
, a source-follower circuit
78
connected to the output terminal of the level shifting circuit
76
, the transmission line
22
which has its sending end connected to an output terminal
79
of the source-follower circuit
78
, and a terminating resistor
80
which has its one terminal connected to a receiving end of the transmission line
22
and its other terminal connected to the negative power supply V
TT
(−2V).
The N-channel MOS type inverter
72
consists essentially of an N-channel MOS type transistor M
72
and a resistor R
72
in such a configuration that the N-channel MOS type transistor M
72
has its gate connected to the input terminal
71
, its source connected to the ground (GND), and its drain connected via the resistor R
72
to the positive power supply V
DD
. The clamp circuit
74
consists essentially of a PN-junction diode D
74
and a resistor R
74
in such a configuration that the PN-junction diode D
74
has its cathode connected via the resistor R
74
to the output terminal of the N-channel MOS type inverter
72
. The level shifting circuit
76
consists essentially of an NPN bipolar transistor Q
76
A, a resistor R
76
A, an NPN bipolar transistor Q
76
B, and a resistor R
76
B which are connected in series between the positive power supply V
DD
and the negative power supply V
EE
. The base of the NPN bipolar transistor Q
76
A is connected to the output terminal of the N-channel MOS type inverter
72
, while the base of the NPN bipolar transistor Q
76
B is supplied with a V
cs
signal. The V
cs
signal consists essentially of a bias voltage for a constant current source. An NPN bipolar transistor Q
78
which constitutes the source-follower cir
Foley & Lardner
NEC Corporation
Tan Vibol
Tokar Michael
LandOfFree
Level converting method and circuit having an intermediate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Level converting method and circuit having an intermediate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Level converting method and circuit having an intermediate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2595344