Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-01-26
2002-04-30
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S070000
Reexamination Certificate
active
06380761
ABSTRACT:
The invention relates to a level converter for the converting of a first digital signal having a first voltage range into a second digital signal having a second voltage range comprising an amplifier having an input for receiving the first digital signal and an output for supplying the second digital signal, a series arrangement for controlling the slew-rate of the second digital signal which comprises at least a first capacitor and a second capacitor and which is coupled between the output and the input of the amplifier, and voltage controlling means for controlling the voltages across the at least first and second capacitors.
Such a level converter is known from the general state of the art as shown in FIG.
1
. It must be stated that where the wordings “level of a signal” is used, the word “level” has to be interpreted as the maximum possible voltage value of the signal minus the minimum possible voltage value of the signal. (The minimum possible voltage level is usual close to zero volt.) The known level converter comprises a field effect transistor T
0
having a gate for receiving a first digital signal U
1
, a source connected to a supply reference terminal GND and a drain connected to an output terminal
2
for delivering a second digital signal U
2
. The output terminal
2
is connected, via a load Z
L
, to a supply voltage supplied by a supply voltage source SPL
LV
of the level converter. The load Z
L
may also be replaced by various kinds of circuitries for example by a current source. A series arrangement of a first and a second capacitor C
1
, C
2
is connected between the drain and the gate of the field effect transistor T
0
. The first and the second capacitors C
1
, C
2
are respectively shunted by a first and a second shunt resistor R
1
, R
2
. The known level converter further comprises a pré-drive circuit PDC having a first supply reference connected to the supply reference terminal GND, a second supply reference connected, via a series resistor R
PDC
, to a pré-drive supply voltage source SPL
PDC
, an input coupled to an input terminal
1
of the level converter, and an output coupled to the gate of the field effect transistor T
0
.
The principle operation of the known level converter is as follows. The input
1
is connected to any digital circuit which supplies a digital signal of which the voltage level must be adapted, normally to a higher voltage level. This digital signal is buffered by the pré-drive circuit PDC which delivers a first digital signal U
1
, of the level converter. The level of the first digital signal U
1
is determined by the value of the supply voltage supplied by the pré-drive supply voltage source SPL
PDC
. The field effect transistor T
0
in conjunction with the load Z
L
converts the first digital signal U
1
into the second digital signal U
2
. The level of the second digital signal U
2
is determined by the value of the supply voltage supplied by the supply voltage source SPL
LV
of the level converter.
Many known level converters have the disadvantage that they cause electromagnetic interference and/or groundbounce in other digital circuits, if applied in an integrated circuit. This has been solved in a way as in the known level converter as shown in FIG.
1
. In fact two measures are normally implemented. The first measure is the application of the series resistor R
PDC
for limiting the current which can be supplied by the output of the pré-drive circuit PDC. The second measure is the application of a capacitive path connected between the drain and the gate of the field effect transistor T
0
. By so doing the slew-rate of the second digital signal U
2
is controlled and is approximately equal to the quotient of the value of the limited current and the value of the capacitance formed by the capacitive path. The application of the series resistor R
PDC
is optional because the current is also limited by the pré-drive circuit itself. However if the series resistor R
PDC
is omitted the value of the limited current can generally not be predicted very accurately. The simplest implementation for the capacitive path would be a single capacitor connected between the drain and the gate of the field effect transistor T
0
. However if applied in an integrated circuit this can lead to the problem that the voltage across the single capacitor is higher than permitted. In the known level converter as shown in
FIG. 1
this problem is solved by forming the capacitive path by a series arrangement of a first and a second capacitor C
1
, C
2
. Since the common node of the first and the second capacitor may not be a DC-floating node the first and the second capacitor C
1
, C
2
are shunted respectively by the first and the second shunt resistor R
1
, R
2
.
A problem of the known level converter is that the shunt resistors R
1
and R
2
increase the static power dissipation of the level converter.
It is an object of the invention to provide a level converter which has a reduced static power dissipation.
To this end, according to the invention, the level converter of the type defined in the opening paragraph is characterized in that the voltage controlling means comprises at least one voltage source for supplying a separate bias voltage to each internal node of the series arrangement, and in that the value of the separate bias voltage or the values of the separate bias voltages is/are dependent on the values of the first and the second digital signals.
The invention is based on the insight that in the known level converter as shown in
FIG. 1
the increase of the static power dissipation is caused by the fact that the first and the second resistors form together a DC-path between the drain and the gate of the field effect transistor T
0
. In principle this is not necessary. Only the internal node(s) (In
FIG. 1
there is only one internal node N
1
) must be biased because otherwise the/these internal node(s) would be DC-floating nodes. For clarity it is stated that the outer nodes of the series arrangement for controlling the slew-rate of the second digital signal U
2
may not be interpreted as internal nodes of said series arrangement.
When the state of the first and second digital signal changes, the voltage on the internal nodes have to be changed as well. In the known level converter this occurs automatically by the fact that the series arrangement of the first and the second resistors form a voltage divider. Since a level converter according to the invention do not have such a voltage divider the voltages on the internal nodes must be adapted in a different way. For this reason the at least one voltage source for supplying the bias voltage to the internal node or for supplying separate bias voltages to each internal node must be made dependent on the values of the first and the second digital signals.
An embodiment of the invention may be characterized in that a bias resistor is arranged in series with at least one of the at least one voltages sources. If the aforementioned dependency of the at least one voltage source is not optimal (which in practice is nearly always the case) then the dynamic power dissipation of the level converter will be increased. This increase of the dynamic power dissipation is reduced by the application of a bias resistor to each internal node of the series arrangement for controlling the slew-rate of the second digital signal U
2
. The value of the bias resistors can however not be chosen arbitrarily high because a too high value of the bias resistor will cause a too inaccurate control of the voltages of the internal nodes. It may not always be necessary to physically implement the bias resistors because the internal resistances of the voltage source or sources for supplying the bias voltage or voltages to each internal node may well serve as said bias resistors.
A further embodiment of the invention may be characterized in that switching means is/are arranged in series with the at least one voltages sources. By so doing a type of class C biasing of each internal node can be accomplished by a proper functioning of
Chang Daniel D.
Tokar Michael
U.S. Philips Corporation
Waxler Aaron
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