Level converter circuit

Details Level converter circuit Level converter circuit

2001-03-20

2002-10-15

Lee, Michael G. (Department: 2876)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S063000, C326S080000, C326S083000

Reexamination Certificate

active

06466054

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-086385, filed Mar. 27, 2000; and No. 2000-325047, filed Oct. 25, 2000, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a level converter circuit operated by using a plurality of power supplies.
Recently, the number of semiconductor elements formed on a chip has significantly increased. Several hundreds of millions of semiconductor elements are integrated per chip in a gigabit-order semiconductor memory, and several tens of thousands to tens of millions of semiconductor elements are integrated per chip in a 64-bit microprocessor. The number of semiconductor elements formed on a chip can be improved by reducing the size of semiconductor elements. Currently, in a 1-Gbit DRAM (Dynamic Random Access Memory), MOS transistors with a gate length of 0.15 &mgr;m are used. To further increase the number of semiconductor elements formed on a chip, MOS transistors with a gate length of 0.1 &mgr;m or less will need to be used.
In the above fine patterned MOS transistor, hot carriers deteriorate the transistor and an insulating film is destroyed by TDDB (Time Dependent Dielectric Breakdown). Further, a junction breakdown voltage of a source and drain is lowered when the impurity concentrations of a substrate region and a channel region are increased in order to suppress a lowering in a threshold voltage due to a reduction in the channel length. Lowering a power supply voltage keeps the reliability of the fine patterned element high. That is, weakening a lateral electric field between the source and the drain prevents hot carriers and weakening the vertical electric field between the gate and the bulk prevents TDDB. Further, by lowering the power supply voltage, reverse bias voltages applied to a junction between the source and the bulk and a junction between the drain and the bulk are lowered so as to cope with a lowering in a withstand voltage.
Recently, the market for portable information devices has remarkably increased. Most of the portable information devices employ a lightweight power supply, such as a lithium ion battery having a high energy density. However, the three volts (3V) of the lithium ion battery is higher than the withstand voltage of the fine patterned MOS transistor. Therefore, when the lithium ion battery is applied to a circuit comprising the fine patterned transistor, a power supply voltage converter must be used to reduce the voltage. The power consumed during the operation of a CMOS circuit used in a logic circuit is not only proportional to an operational frequency, but also proportional to the square of the power supply voltage. Therefore, reducing the power supply voltage significantly lowers the power consumption in the chip.
Therefore, to use a portable device for a longer period of time, it is required to develop a battery with high energy density, a power supply conversion circuit with high efficiency, and an integrated circuit operated at a low voltage. It is desirable to use the lowered power supply voltage in a base-band LSI and microprocessor with large power consumption from the viewpoint of attainment of the low power consumption.
In the portable information device, it is necessary to use a memory device such as a DRAM or SRAM in addition to a logic circuit. The DRAM is designed to attain a sufficient charge amount of a cell to enhance a soft error resistance and the SRAM is designed to prevent a lowering in the operation speed at the time of the low-voltage operation. Therefore, there are no significant measures for making the power consumption low as in the logic circuit, and at present, elements operated on a power supply voltage of approximately 1.75V are put into practice. However, since the power supply voltage of the memory circuit is greatly different from that of the logic circuit, it is necessary to use a multiple power supply construction for supplying various power supply voltages in an LSI having a memory circuit and a logic circuit.
FIG. 1
shows the construction of a semiconductor integrated circuit
405
for a portable information device having a memory circuit and logic circuit integrated on one chip and a power supply system thereof. The circuit of
FIG. 1
includes a lithium battery (lithium ion secondary battery)
400
, a power supply conversion circuit
401
, a logic circuit
402
, an on-chip memory circuit
403
, and a level converter
404
. The output power supply voltage 3V of the lithium battery
400
is converted into 0.5V by the power supply conversion circuit
401
to supply a 0.5V power supply voltage to the logic circuit
402
. Since the on-chip memory circuit
403
requires a power supply voltage of 1V or more for its operation, the output power supply voltage 3V of the lithium battery
400
is supplied directly to the memory circuit
403
. The 3V power supply voltage and 0.5V power supply voltage are supplied to the level converter
404
, which connects the memory circuit
403
and logic circuit
402
.
With the construction shown in
FIG. 1
, setting the power supply voltage of the logic circuit
402
to 0.5V can lower the power consumption at an operation time. However, when the power supply voltage of a general CMOS circuit is simply lowered from 3V and operated on a power supply voltage of 2V, , the operation speed of the device is lowered or the device will not correctly operate. To solve the above problem, it is necessary to lower the threshold voltage of the MOS transistor with a lowering in the power supply voltage. For example, to construct a logic circuit that operates on a low power supply voltage of 0.5V, it is necessary to use an FET having a threshold voltage of 0.1V to
0
.2V in the absolute value that is equal to approximately ⅓ of the threshold voltage of the conventional FET.
However, if the above threshold value is used, a leakage current of the FET at the OFF time is greatly increased, and as a result, the power consumption of the device at the standby time is greatly increased and the semiconductor integrated circuit for the portable information device cannot be suitably used as it is.
FIG. 2
shows the construction of a semiconductor integrated circuit and a power supply system thereof constructed by taking the above problem into consideration. In
FIG. 2
, four kinds of power supply voltages (VDD, VD
1
, VS
1
, VSS) including a ground potential are supplied to a semiconductor integrated circuit
506
. A 3V power supply voltage (VDD) supplied from a lithium battery
500
, a ground potential (VSS), and VD
1
and VS
1
supplied from a power supply conversion circuit
501
are supplied to a logic circuit
502
integrated on a chip in the semiconductor integrated circuit
506
. In this case, a potential difference between the logic circuit power supply voltage VD
1
and the logic circuit ground voltage VS
1
is set at 0.5V.
With the above construction, the logic circuit
502
is operated by use of two voltages VD
1
and VS
1
to lower the power consumption at the operation time. Further, in the standby state, the well potential of a p-channel MOSFET
509
is set to VDD from VD
1
by setting a p-channel MOSFET
507
to the ON state and the well potential of an n-channel MOSFET
510
is set to VSS from VS
1
by setting an n-channel MOSFET
508
to the ON state. As a result, the absolute values of the threshold voltages of the MOSFETs
509
and
510
in the logic circuit at the standby time are increased and the leakage current at the OFF time thereof is reduced, thereby making it possible to lower the power consumption in the standby state.
As to the power supply for on-chip memory circuits
503
,
504
and
505
, the following three constructions are considered.
1) The chip power supply voltage VDD and chip ground potential VSS supplied from the lithium battery are used.
2) The logic circuit power supply voltage VD
1
and chip ground potential VSS are used.
3) The

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