Level conversion output circuit with reduced power consumption

Details Level conversion output circuit with reduced power consumption Level conversion output circuit with reduced power consumption

1994-04-25

1995-05-16

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 21, 326121, H03K 190948

Patent

active

054163684

ABSTRACT:
A level conversion output circuit includes two level conversion circuits for "high" and "low" logic signals, each of which includes a first CMOS inverter operating between an internal power supply of 3.3 V and ground, and a second CMOS inverter operating between an external power supply of 5 V and ground. One of the level conversion circuits is provided with an additional p-MOS transistor so that a 5.0 V voltage is applied to a gate of a p-MOS transistor of the second CMOS inverter from the external power supply through the additional p-MOS transistor, when the p-MOS transistor of the second CMOS inverter is controlled to be turned off.

REFERENCES:
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4574273 (1986-03-01), Atsumi et al.
patent: 4587446 (1986-05-01), Okumura
patent: 4857763 (1989-08-01), Sakurai et al.
patent: 5151616 (1992-09-01), Komuro

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