Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2005-09-21
2008-10-07
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S063000, C326S081000, C326S083000, C327S033000
Reexamination Certificate
active
07432740
ABSTRACT:
In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.
REFERENCES:
patent: 5469080 (1995-11-01), Son
patent: 6480050 (2002-11-01), Barnes
patent: 5-308274 (1993-11-01), None
patent: 6-209256 (1994-07-01), None
patent: 7-86913 (1995-03-01), None
Barnie Rexford
Buchanan & Ingersoll & Rooney PC
Renesas Technology Corp.
Tabler Matthew C
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