Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-02-28
2002-04-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S063000, C326S083000, C326S058000, C326S095000, C326S098000, C327S333000
Reexamination Certificate
active
06373283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level conversion circuit converting the voltage amplitude of an input signal to a larger voltage amplitude, and a semiconductor device and a display unit employing the same.
2. Description of the Background Art
In recent years, a chip, referred to as a system-on-silicon chip, formed by loading a microprocessor or a memory on the same chip as a logic circuit is developed as an integrated circuit employing bulk silicon. Following such development, a technique of forming a number of types of circuits on a single chip with the finest possible design rules is now in the process of development.
However, the design rules vary with the types of the circuits, and hence circuits having different design rules must inevitably be integrated. Consequently, a plurality of circuits operating with different supply voltages are mixedly formed in a single chip. In this case, the voltages must be level-converted in an interface part between the different circuits.
Improvement of a high-speed property is attained by mixedly forming a plurality of circuits of different types on the same chip. Therefore, a level conversion circuit performing level conversion of voltages between the different circuits must also have high-speed operability.
Thin-film transistors of polycrystalline silicon are employed for a display device such as a liquid crystal display unit or an organic EL (electroluminescence) device. When provided on the same substrate as such a display device, the level conversion circuit is also formed by thin-film transistors of polycrystalline silicon.
In steps of fabricating transistors, device characteristics such as threshold voltages vary. Particularly in thin-film transistors of polycrystalline silicon, variations of device characteristics such as threshold voltages are extremely large. Thus, awaited is a level conversion circuit capable of reliably operating also when device characteristics such as threshold voltages of thin-film transistors vary.
Such a display device requires a level conversion circuit capable of operating at a high speed also when an input signal having a small amplitude is supplied in view of reduction of power consumption and improvement in definition.
FIG. 45
is a circuit diagram showing a first exemplary conventional level conversion circuit
800
.
The level conversion circuit
800
shown in
FIG. 45
includes two p-channel MOSFETs (metal-oxide semiconductor field-effect transistors)
801
and
802
and two n-channel MOSFETs
803
and
804
.
The p-channel MOSFETs
801
and
802
are connected between a power supply terminal receiving a supply potential VDD and output nodes N
11
and N
12
respectively, while the n-channel MOSFETs
803
and
804
are connected between the output nodes N
11
and N
12
and a ground terminal respectively. The gates of the p-channel MOSFETs
801
and
802
are cross-coupled to the output nodes N
12
and N
11
respectively. The gates of the n-channel MOSFETs
803
and
804
are supplied with mutually complementarily changing input signals CLK
1
and CLK
2
respectively.
When the input signal CLK
1
goes high and the input signal CLK
2
goes low, the n-channel MOSFET
803
is turned on and the n-channel MOSFET
804
is turned off. Thus, the p-channel MOSFET
802
is turned on and the p-channel MOSFET
801
is turned off. Consequently, an output potential Vout of the output node N
12
increases. When the input signal CLK
1
goes low and the input signal CLK
2
goes high, on the other hand, the output potential Vout of the output node N
12
decreases.
In this case, the voltage amplitudes of the input signals CLK
1
and CLK
2
must be larger than the threshold voltages Vtn of the n-channel MOSFETs
803
and
804
, in order to turn on the n-channel MOSFETs
803
and
804
.
Therefore, the level conversion circuit
800
shown in
FIG. 45
is employed when the voltage ratio between input and output signals is small.
For example, this level conversion circuit
800
is effective when converting a 3 V-system signal to a 5 V-system signal, converting a 2.5 V-system signal to a 3 V-system signal or converting a 1.8 V-system signal to a 2.5 V- or 3.3 V-system signal.
FIG. 46
is a circuit diagram showing a second exemplary conventional level conversion circuit
810
.
The level conversion circuit
810
shown in
FIG. 46
includes a bias circuit
811
, a p-channel MOSFET
812
and an n-channel MOSFET
813
.
The p-channel MOSFET
812
is connected between a power supply terminal receiving a supply potential VDD and an output node N
13
, while the n-channel MOSFET
813
is connected between the output node N
13
and another power supply terminal receiving a prescribed potential VEE. An input signal CLK is supplied to the gate of the p-channel MOSFET
812
and the bias circuit
811
. The bias circuit
811
supplies the input signal CLK to the gate of the n-channel MOSFET
813
while shifting the central level thereof.
When the input signal CLK goes high, the p-channel MOSFET
812
is turned off and the n-channel MOSFET
813
is turned on. Thus, an output potential Vout of the output node N
13
decreases. When the input signal CLK goes low, on the other hand, the p-channel MOSFET
812
is turned on and the n-channel MOSFET
813
is turned off. Thus, the output potential Vout of the output node N
13
increases.
In this case, the bias circuit
811
shifts the central level of the input signal CLK, and hence the level conversion circuit
810
operates also when the voltage amplitude of the input signal CLK is smaller than the threshold voltage Vtn of the n-channel MOSFET
813
.
FIG. 47
is a circuit diagram showing a third exemplary conventional level conversion circuit
820
.
The level conversion circuit
820
shown in
FIG. 47
includes a clamping circuit
821
and a current mirror amplifier
822
.
The current mirror amplifier
822
includes two p-channel MOSFETs
831
and
832
and two n-channel MOSFETs
833
and
834
. The p-channel MOSFETs
831
and
832
are connected between power supply terminals receiving a supply potential VDD and output nodes N
14
and N
15
respectively. The n-channel MOSFETs
833
and
834
are connected between the output nodes N
14
and N
15
and ground terminals respectively. The gates of the p-channel MOSFETs
831
and
832
are connected to the output node N
14
. The clamping circuit
821
supplies mutually complementarily changing input signals CLK
1
and CLK
2
to the gates of the n-channel MOSFETs
833
and
834
while shifting the central levels thereof.
When the input signal CLK
1
goes high and the input signal CLK
2
goes low, the n-channel MOSFET
833
is turned on and the n-channel MOSFET
834
is turned off. Thus, the p-channel MOSFETs
831
and
832
are turned on. Consequently, an output potential Vout of the output node N
15
increases. When the input signal CLK
1
goes low and the input signal CLK
2
goes high, on the other hand, the output potential Vout of the output node N
15
decreases.
In this case, the clamping circuit
821
shifts the central levels of the input signals CLK
1
and CLK
2
, and hence the level conversion circuit
820
can operate also when the voltage amplitudes of the input signals CLK
1
and CLK
2
are smaller than the threshold voltages Vtn of the n-channel MOSFETs
833
and
834
.
FIG. 48
is a circuit diagram showing a fourth exemplary conventional level conversion circuit
840
.
The level conversion circuit
840
shown in
FIG. 48
includes a clamping circuit
841
and a PMOS cross-coupled amplifier
842
.
The PMOS cross-coupled amplifier
842
includes two p-channel MOSFETs
851
and
852
and two n-channel MOSFETs
853
and
854
. The p-channel MOSFETs
851
and
852
are connected between power supply terminals receiving a supply potential VDD and output nodes N
16
and N
17
respectively, while the n-channel MOSFETs
853
and
854
are connected between the output nodes N
16
and N
17
and ground terminals respectively. The gates of the p-channel MOSFETs
851
and
852
are cross-coupled t
Armstrong Westerman & Hattori, LLP.
Sanyo Electric Co,. Ltd.
Tan Vibol
Tokar Michael
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