Level conversion circuit and serial/parallel conversion...

Details Level conversion circuit and serial/parallel conversion... Level conversion circuit and serial/parallel conversion...

2006-11-21

2006-11-21

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000

Reexamination Certificate

active

07138831

ABSTRACT:
A MOS capacitor receiving a clock signal complementary to a sampling clock signal is provided at an input of a clocked inverter that is activated after sampling an input signal to perform level conversion. A charge pump operation of the MOS capacitor is performed in parallel with the activation of the clocked inverter. The power consumption of and the area occupied by a level conversion circuit converting a voltage amplitude of the input signal are reduced without deteriorating a high-speed operating characteristics.

REFERENCES:
patent: 5581506 (1996-12-01), Yamauchi
patent: 6590423 (2003-07-01), Wong
patent: 7006068 (2006-02-01), Haga
patent: 2001-320268 (2001-11-01), None
patent: 2002-251174 (2002-09-01), None
patent: 2002-358055 (2002-12-01), None
patent: 2003-115758 (2003-04-01), None

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