Level conversion circuit

Electronic digital logic circuitry – Interface – Logic level shifting

Reexamination Certificate

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Details

C326S080000, C326S081000

Reexamination Certificate

active

07078934

ABSTRACT:
The source of a p-channel MOSFET of a level conversion unit is connected to a supply terminal which receives supply voltage VDD. The drain is connected to an output node NO and the gate is connected to an input node I2. The source of a n-channel MOSFET is connected to an input node I2, the drain is connected to the output node NO and the gate is connected to the supply terminal which receives the supply voltage VDD. Input signals CLK1and CLK2change complementarily and difference of voltage between the high level and low level of the signals is smaller than difference between the supply voltage VDD and the ground voltage.

REFERENCES:
patent: 4486670 (1984-12-01), Chan et al.
patent: 5387828 (1995-02-01), Nakano
patent: 6344764 (2002-02-01), Tanzawa
patent: 1-176115 (1989-07-01), None
patent: 1-231418 (1989-09-01), None
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patent: 03-291013 (1991-12-01), None
patent: 4-97616 (1992-03-01), None
patent: 6-37624 (1994-02-01), None
patent: 6-177744 (1994-06-01), None
patent: 6-204850 (1994-07-01), None
patent: 9-205351 (1997-08-01), None
patent: 2000-286694 (2000-10-01), None
patent: 2001-320268 (2001-11-01), None
Office Action for Corresponding Korean Patent Application 10-2004-7000337 dated Aug. 31, 2005.

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