Level 2 cache architecture for multiprocessor with...

Details Level 2 cache architecture for multiprocessor with... Level 2 cache architecture for multiprocessor with...

2001-08-17

2004-05-18

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S135000, C711S145000

Reexamination Certificate

active

06738864

ABSTRACT:

This application claims priority to European Patent Application Serial No. 00402331.3, filed Aug. 21, 2000 and to European Application Serial No. 00403537.4, filed Dec. 15, 2000 U.S. patent application Ser. No. 09/932,651 is incorporated herein by reference.
FIELD OF THE INVENTION
This invention generally relates to microprocessors, and more specifically to improvements in cache memory access circuits, systems, and methods of making.
BACKGROUND
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a cache with at least a first request port and a plurality of lines with an associated plurality of tags. A request for cache access includes an address value representative of an address of a requested data and a qualifier value. A determination is made to see if data corresponding to the address value provided by a request is present in the cache by examining a tag entry; a hit is indicated if an address field of the tag entry matches a portion of the address value provided by the first request. Otherwise, a miss is indicated. If a miss occurs, data corresponding to the address value provided by the request is retrieved and stored in a line of the cache associated with the tag, while a portion of the address is stored in the address field of the first tag, and the qualifier value provided by the request is stored in a qualifier field of the tag. An indicator is asserted if the address field of the tag matches the address provided with the request but the qualifier field does not match a qualifier value provided with the request. In one embodiment, if a qualifier field mismatch is indicated, then an error is reported. In another embodiment, a qualifier field mismatch is treated as a miss.
In another embodiment, separate valid bits are associated with the address field and the qualifier field of the tag. If a qualifier field valid bit is not set, then the qualifier field is ignored.
The qualifier field represents a task-ID indicative of a software task that initiated the request. In another embodiment, the qualifier field represents a resource-ID indicative of a hardware resource that initiated the first request. In another embodiment, there are two or more qualifier fields that may hold a task-ID and a resource-ID, or other types of access qualifiers.
In another embodiment, a digital system is provided with a cache that has a request port, a data array having a plurality of lines for holding data, and a tag array having a plurality of lines for holding a plurality of tags. Each line of the tag array is associated with a particular line of the data array. Each line of the tag array has an address field and qualifier field. Hit/miss circuitry has a first input connected to the tag array to receive an address value from the address field and a second input connected to the request port to receive a portion of a proffered address received by the request port. Comparison circuitry has a first input connected to the tag array to receive a stored qualifier value from the qualifier field and a second input connected to the request port to receive a proffered qualifier value received by the request port. The cache is a level two cache, but in other embodiments the cache may be a first level or a higher level cache. In another embodiment, there are additional qualifier fields and additional comparison circuitry to compare the additional qualifier field(s) to proffered qualifier values.
In another embodiment, a first level cache embodying the present invention may make requests to a second level cache that also embodies the present invention.


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patent: 6119167 (2000-09-01), Boyle et al.
patent: 2003/0163648 (2003-08-01), Smith
Texas Instruments Incorporated, S/N: 09/591,537, filed Jun. 9, 2000,Smart Cache.

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