Length matrix generator for register transfer level code

Details Length matrix generator for register transfer level code Length matrix generator for register transfer level code

2002-12-31

2004-06-29

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06757885

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method of avoiding congestion inherent in register transfer level (RTL) code used in the design of integrated circuits.
2. Description of the Prior Art
Previously, congestion resulting from routing signals in an integrated circuit has only been estimated at the netlist cell placement stage, late in the design cycle. Multiple iterations and manually generated alternatives in the physical design phase are typically used to resolve timing and congestion problems.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method of generating a length matrix for register transfer level code includes steps for receiving as input register transfer level code, an I/O block list, a plurality of compile units, and a user defined hierarchical depth; mapping the register transfer level code to a design library, generating a connectivity matrix for the plurality of compile units, generating a priority list of interconnections from the connectivity matrix, generating placement coordinates for the compile units from the priority list of interconnections and the connectivity matrix, and generating as output at least one of the connectivity matrix and the placement coordinates.
In another aspect of the present invention, a computer program product for estimating congestion for register transfer level code includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.


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Focus Report: Logic Synthesis and Silicon Compilation Tools by Steven E. Schulz, Eedesign; http://www.eedesign.com/eedesign/focusreport9605.html.

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