Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
1999-09-30
2001-08-28
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
Reexamination Certificate
active
06281028
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for aligning an integrated circuit for analysis.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuit dies have been tested using methods including accessing circuitry or devices within the die. In order to access portions of circuitry in the integrated circuit die it is sometimes necessary to align the die with equipment such as a milling device, a test fixture, or other test equipment. For example, in flip-chip type dies, transistors and other circuitry are located in a very thin epitaxially-grown silicon layer in a circuit side of the die. The circuit side of the die is arranged facedown on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip. Such back side access often requires milling through the back side and probing certain circuit elements. The milling and probing processes may potentially damage elements in the integrated circuit if not properly aligned. The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits are impediments to the growth and improvement of semiconductor technologies. To access the backside circuitry, it is necessary to align the circuit with a CAD layout. This is done with alignment markers; however, alignment markers are not visible through silicon from the backside with most tools without substantial thinning.
SUMMARY OF THE INVENTION
The present invention is directed to a method for manufacturing and analyzing a semiconductor die that improves the ability to align the die for post-manufacturing testing. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor die having a light-emitting diode (LED) is formed. The semiconductor die has a circuit side opposite a back side. A terminal is formed in the back side, and a conductor is formed extending from the terminal and toward the circuit side. A LED is formed within the semiconductor die and coupled to the conductor. The LED is activated via the terminal and used for aligning the die for analysis. The activated LED provides a detectable reference point from which to align the die for analysis, such as for milling or testing defective dies.
According to another example embodiment of the present invention, a system is arranged to analyze a semiconductor die having a LED formed within the die and a conductor coupled to the LED and extending to a terminal on the surface of the die. A power source is coupled to the terminal to activate the LED via the conductor. A radiation detection device is arranged to detect radiation emitted from the activated LED. Using the detected radiation, the die is aligned in a test fixture. The system further includes test equipment arranged to analyze the die once it has been aligned.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5834323 (1998-11-01), Ghafghaichi et al.
patent: 5998232 (1999-12-01), Maruska
Birdsley Jeffrey D.
Bruce Michael R.
Davis Brennan V.
Goruganthu Rama R.
Ring Rosalinda M.
Advanced Micro Devices , Inc.
Christianson Keith
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