Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-12
2004-04-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S052000, C257S077000, C257S524000
Reexamination Certificate
active
06717212
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the manufacture of semiconductor structures and, more specifically, relates to the manufacture of semiconductor-on-insulator (SOI) structures.
BACKGROUND ART
Semiconductor-on-insulator (SOI) structures have several advantages over conventional bulk substrates: the elimination of latch-up, reduced short-channel effects, improved radiation hardness, dynamic coupling, lower parasitic junction capacitance, and simplified device isolation and fabrication. Such advantages allow semiconductor device manufacturers to produce low-voltage low-power high-speed devices thereon. For example, metal-oxide semiconductor field effect transistors (MOSFETs) are commonly formed on SOI structures. However, MOSFETs formed on such SOI structures suffer from a floating body effect (FBE) and self-heating.
Unlike bulk silicon MOSFETs, an SOI MOSFET is usually electrically floating in relation to the substrate. In a non-fully depleted MOSFET, carriers (holes in nMOSFETs and electrons in pMOSFETs) generated by impact ionization accumulate near the source/body junctions of the MOSFET. Eventually, sufficient carriers will accumulate to forward bias the body with respect to the source thus lowering the threshold voltage through the body-bias effect. Extra current will start flowing resulting in a “kink” in the I-V characteristics. The extra current flow reduces the achievable gain and dynamic swing in analog circuits, and gives rise to an abnormality in the transfer characteristics in digital circuits. Additionally, the FBE causes higher device leakages and undesirable transient effects.
One attempted solution to solve problems due to the FBE is to provide a contact to the body for hole current collection. However, currently available hole collection schemes, including the use of a side-contact or a mosaic source are very inefficient and consume significant amounts of wafer area.
Another problem associated with SOI structures is self-heating. Self-heating due to poor thermal conductivity of the buried oxide layer, in addition to causing circuit performance degradation, also increases device failure due to Joule heating. Further, severe localized silicon heating can result in junction melting and silicon melt filament formation. Such junction melting and filament formation may cause electrical shorts among the gate, source, drain and body of the MOSFET, thus resulting in device failure.
The thermal conductivity of the insulator materials determines in part how efficiently the heat is dissipated. The heat generated in the device regions propagates vertically to the semiconductor substrate via the BOX layer, SiO
2
in conventional silicon-on-insulator structures, and laterally to the oxide isolation trenches in the non-device regions. The thermal conductivity of SiO
2
is about 1.7 W/mK, whereas the thermal conductivity of the pure Si substrate is about 170 W/mK. A material with a lower thermal conductivity value means the material dissipates heat less effectively than the material with a higher value. Thus, the lower thermal conductivity of SiO
2
, the BOX layer, does not propagate efficiently the heat generated by the SOI devices to the substrate through the BOX layer. Therefore, the SiO
2
BOX layer inhibits cooling of the SOI devices and causes severe self-heating effects, which prevents the maximum available power consumption from increasing.
Additionally, this increases the maximum interconnect temperature, and makes conduction cooling through the source, drain, and interconnects important. In addition, the device mobility is reduced as a result of the higher channel temperature, reducing the maximum drain saturation current and causing a negative differential conductance in the saturation region. Thermal protection schemes designed for SOI circuits have been proposed using contact plugs in diodes. Although effective in dissipating heat, contact plugs consume large wafer area, introduce large delays, and increase manufacturing costs.
Therefore, there exists a strong need in the art for an SOI structure with a buried insulator material that is leaky enough to bleed off the extra carriers into a channel of the substrate, has a resistance approximately equal to SiO
2
and thermally conducts heat away from the device at a rate greater than a conventional SiO
2
insulator layer at room temperature.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive insulator material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer. The SOI structure has an active region defined laterally by isolation regions such as shallow trench isolation (STI) regions and vertically by the LTCIM layer.
According to another aspect of the invention, the invention is a method of fabricating a semiconductor-on-insulator (SOI) structure having a LTCIM layer disposed between a semiconductor substrate and a semiconductor layer. The method includes the steps of depositing an LTCIM layer on a first semiconductor substrate and depositing an LTCIM layer on a second semiconductor substrate. Further, the method includes the step of creating a zone of weakness under a surface of one of the semiconductor substrates. Next, the method requires the placing of one of the semiconductor substrates on top of the other semiconductor substrate such that the LTCIM layer of the first semiconductor substrate is in contact with the LTCIM layer of the second semiconductor substrate. The method also includes the step of breaking the zone of weakness of the one semiconductor substrate and repairing a damaged surface resulting from the breaking of the zone of weakness of the one semiconductor substrate.
According to another aspect of the invention, the invention is a method of fabricating an SOI structure as described above. However, the method step of repairing the surface resulting from the breaking of the zone of weakness further includes the step of polishing the surface in order to remove residual weak zone damage.
According to another aspect of the invention, the invention is a method of fabricating an SOI structure as described in the first method above. The method further includes the additional step of fusing the LTCIM layer of the first semiconductor substrate with the LTCIM layer of the second semiconductor substrate.
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An Judy Xilin
En William George
Ju Dong-Hyuk
Krishnan Srinath
Krivokapic Zoran
Advanced Micro Devices , Inc.
Flynn Nathan J.
Renner , Otto, Boisselle & Sklar, LLP
Sefer Ahmed N.
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