Leakage verification for flash EPROM

Details Leakage verification for flash EPROM Leakage verification for flash EPROM

1989-03-14

1989-08-22

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365201, 371 28, 371 67, G11C 1300

Patent

active

048602612

ABSTRACT:
A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.

REFERENCES:
patent: 4797586 (1989-01-01), Lee et al.

Affiliated with

Also associated with

Rating

Leakage verification for flash EPROM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Leakage verification for flash EPROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leakage verification for flash EPROM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2420568