Leakage power optimization for integrated circuits

Details Leakage power optimization for integrated circuits Leakage power optimization for integrated circuits

2006-01-31

2006-01-31

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06993737

ABSTRACT:
A method for reducing leakage power in a system comprises determining the static probability for a signal in the system. If the static probability of the signal is in a high power range, then the signal is modified such that the static probability of the modified signal is in a low power range, and such that functionality of the system is not affected. In some embodiments, where the signal is a digital signal, modifying the signal comprises inverting the signal. In some embodiments, where the system comprises a programmable logic device, modifying the signal has no area or performance penalty.

REFERENCES:
patent: 5655109 (1997-08-01), Hamid
patent: 5696694 (1997-12-01), Khouja et al.
patent: 5805459 (1998-09-01), Kapoor
patent: 5838579 (1998-11-01), Olson et al.
patent: 5903476 (1999-05-01), Mauskar et al.
patent: 5949689 (1999-09-01), Olson et al.
patent: 6075932 (2000-06-01), Khouja et al.
patent: 6195630 (2001-02-01), Mauskar et al.
patent: 6345379 (2002-02-01), Khouja et al.
patent: 6674672 (2004-01-01), Forbes et al.
patent: 6687883 (2004-02-01), Cohn et al.
Halter, Jonathan P., “A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits,” IEEE Custom Integrated Circuits Conference, 1997, pp. 475-478, IEEE, 3 Park Avenue, 17th Floor, New York, NY., 10016-5997.
Yeap, Gary, “Practical Low Power Digital VLSI Design,” 1998, pp. 59-72, available from Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061.
Anderson, Jason H., “Active Leakage Power Optimization for FPGAs,” FPGA '04, Feb. 22-24, 2004, Monterey, California, USA, 9 pages, available from janders@eecg.toronto.edu or Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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