Leakage control circuit

Details Leakage control circuit Leakage control circuit

2002-12-13

2004-06-08

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S207000, C365S226000, C365S230060

Reexamination Certificate

active

06747904

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a leakage control circuit, and particularly to a leakage control circuit applied in dynamic random access memories.
2. Description of the Related Art
In order to preserve power consumption and propagation delay, power supplies and threshold voltages are reduced with scaling of the CMOS process. Reductions of the threshold voltages, however, result in sub-threshold leakage currents significantly, so high density memories, such as dynamic random access memories, consume more power and have short retention time.
In deep submicron CMOS process, short channel effect is significant, depletion layers of drains and sources overlap much more, and parasitic bipolar junction transistor of drain-gate-source in MOS transistor enhances the sub-threshold leakage currents.
A fixed reverse bias is applied to substrates, adopted in the prior art, to increase threshold voltage to turn off MOS transistors. In deep submicron CMOS process, this is not sufficient to turn off MOS transistors completely. There is a need for a novel leakage control circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to. prevent leakage currents in MOS transistors, and particularly to turn off switch MOS transistors in a dynamic random access memory.
To achieve the above objects, the present invention provides a leakage control circuit for a dynamic random access memory.
The leakage control circuit includes MOS transistors for monitoring leakage currents, a differential amplifier, resistors, the first, second, third, and fourth resistors, a charge pump, and a word-line driver. The MOS transistors for. monitoring leakage currents are fabricated by the same process, which fabricates the switch MOS transistors in memory cell. The first resistor and the second resistor are in series to form a first voltage divider. The first reference voltage is generated at the junction of the first divider and coupled to the non-inverting input of the differential amplifier. The third resistor and the fourth resistor form a second voltage divider. The second reference voltage is generated at the junction of the second divider and coupled to the inverting input of the differential amplifier. The output of the differential amplifier is coupled to an input of an inverter. The output of the inverter is coupled to an enable terminal of the charge pump. The output of the charge pump is coupled to the word line driver and gates of the MOS transistor, and generates a second voltage.
When the leakage currents in the MOS transistors for monitoring leakage currents are below tolerance, the charge pump is inactive, the second voltage remains at a fixed voltage. When the leakage currents in the MOS transistors for monitoring leakage currents are above tolerance, the charge pump is active, and the second voltage is pulled down with a non-overlap clock signal.
With the second voltage is pulled down, the leakage current in the MOS transistor is reduced. Until the leakage current is less than the tolerance, the charge pump is inactive, and the second remains fixed again.


REFERENCES:
patent: 5337284 (1994-08-01), Cordoba et al.
patent: 5553295 (1996-09-01), Pantelakis et al.
patent: 5946258 (1999-08-01), Evertt et al.
patent: 5969565 (1999-10-01), Naganawa
patent: 6597235 (2003-07-01), Choi
patent: 2002/0064077 (2002-05-01), Kobayashi et al.
patent: 2002/0125936 (2002-09-01), Matsuoka
patent: 2003/0058693 (2003-03-01), Marotta

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