Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1998-04-21
2001-01-23
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S784000, C257S787000
Reexamination Certificate
active
06177722
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit packages.
BACKGROUND ART
In integrated circuit fabrication, a continuing challenge is to manufacture electrical assemblies with greater densities and smaller package size. It is extremely important to utilize available space on a printed circuit board in the most efficient manner possible. The trend in integrated circuit packaging is away from traditional dual-in-line and through-hole packaging and towards surface-mount packages, such as small outline packages, ball grid arrays and chip carrier packages. Surface mounting is a process in which a packaged IC is physically mounted onto the surface of a printed circuit board (PCB), rather than inserting leads into plated holes through the PCB. Package specifications, such as outlines, pin configuration, and dimensions are often defined by industry associations, such as JEDEC.
Most surface-mount devices use leads to mount the chip packages onto the surface of a PCB. Small outline IC packages (SOICs) and quad flat packs (QFPs) frequently use “gull wing” leads, which spread away from the device. The main advantage of the gull wing is that the solder joint can be easily inspected. The disadvantage is that the exposed leads tend to bend and break in handling prior to reflow on the system board. Another disadvantage is that the leads take additional space on the PCB since the leads are spread out.
Another type of leads used are “J leads”, in which the leads are tucked under the device and shaped like the letter “J”. “J-leads” are commonly used on plastic-leaded chip carriers (PLCCs). The advantages of the “J-leads” are that they occupy less board space and that the leads are protected underneath the device. However, this makes it more difficult to test, inspect or repair the device and does not allow for low profile mounting.
Leadless integrated circuit packaging is known in the prior art. U.S. Pat. No. 5,535,101 to Miles et al. discloses a leadless integrated circuit package that uses a ball grid array for mounting to the printed circuit board. A ball grid array mounts to the printed circuit board using solder balls located on the underside of the package. There are some advantages to this arrangement such as the package being smaller in size due to the lack of leads jutting out from the edge of the package. However, there are some disadvantages to the ball grid array (BGA) system. Firstly, the solder joints are hidden beneath the package, making visual inspection and in-situ probe testing virtually impossible. Also, the cost of a BGA system is higher because BGAs have a circuit board that holds the chip and fans out the leads. Although BGAs take less space from an area standpoint, routing traces to them use more PCB layers. This can serve to increase the cost of the overall system.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit package that mounts directly to a PCB, without pins, but has accessible contacts for testing and inspection. The leadless package of the present invention uses contacts on the edge of the package that extend over the solder reflow pads on the end user's board to mount to the printed circuit board. The leadless package has a footprint similar to a standard surface mount package. Because of the method used for mounting, larger silicon die can be used than in the standard packaging. Because there are no leads, the space which would otherwise be used by a lead frame is now useable for containing the silicon device chip.
The leadless array package has a substrate made of the same material as most end user's printed circuit boards so thermal mismatch, which is a common problem with surface mount components, is significantly reduced. Additionally, because the electrical contacts are on the outside perimeter of the leadless array package, inspection and testing of the package can be done much more easily than for packages that have ball-grid array type mounting systems.
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Amkor Chip Arrary brochure, “Chip Array Data Sheet”, Jan., 1997.
Kovats Julius A.
Suciu Paul I.
Atmel Corporation
Jr. Carl Whitehead
McGuire, Jr. John P.
Potter Roy
Schneck Thomas
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