Boots – shoes – and leggings
Patent
1996-10-18
1998-12-01
Ngo, Chuong Dinh
Boots, shoes, and leggings
364749, G06F 700, G06F 738
Patent
active
058448268
ABSTRACT:
A leading zero counter or anticipator is described herein which uses a 36-bit-wide bus. The bus can handle four 8 or 9-bit words, two 16-bit words, or one 32-bit word. The leading zero counter has an encoder section, a logic section, and a multiplexer section. Four encoders each receive a separate group of bits. A logic circuit receives the encoded signals and generates the leading zero count(s) for the binary number(s) on the 36-bit bus. The logic circuit is able to simultaneously generate four leading zero counts if the word size is 8 or 9 bits, two leading zero counts if the word size is 16 bits, or one leading zero count if the word size is 32 bits. A multiplexer connected between the logic circuit and a 36-bit output bus receives a control signal that indicates the word size of either 8, 9, 16, or 32 bits and applies the appropriate leading zero counts from the logic circuit to the appropriate bit positions on the output bus.
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Ngo Chuong Dinh
Ogonowsky Brian D.
Samsung Electronics Co,. Ltd.
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