Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
1999-11-03
2001-03-27
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S796000, C257S712000, C257S675000, C257S699000, C257S693000, C257S730000, C257S733000, C257S732000
Reexamination Certificate
active
06208020
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a resin-molded semiconductor device in which semiconductor chip, leadframe and so on are molded with a resin encapsulant. In particular, the present invention relates to an improved device with the backside of a die pad exposed to radiate heat from a built-in power electronic device more efficiently.
In recent years, to catch up with rapidly advancing downsizing of electronic units, it has become increasingly necessary to assemble semiconductor components for those electronic units at a higher and higher density. Correspondingly, sizes and thicknesses of the semiconductor components such as resin-molded semiconductor devices, in which semiconductor chip, leadframe and so on are molded with a resin encapsulant, have also been noticeably reduced. Examples of resin-molded semiconductor devices accomplishing these objects include a so-called “quad flat non-leaded (QFN)” package. From the QFN package, outer leads, which are usually provided to protrude laterally out of a package, are eliminated. Instead, external electrodes to be electrically connected to a motherboard are provided on the backside of the QFN package.
Particularly when a power electronic device is built in a semiconductor chip, the resin-molded semiconductor device should have its size or thickness reduced while taking its heat radiation properties into account. Thus, a QFN package for a power electronic device (hereinafter, simply referred to as a “power QFN package”) has intentionally exposed the backside of a die pad, on which a semiconductor chip is mounted, not covered with a resin encapsulant. Hereinafter, structure and manufacturing method of a conventional power QFN package will be described.
FIG.
18
(
a
) is a perspective view of a conventional power QFN package; FIG.
18
(
b
) is a cross-sectional view thereof taken along the line XVIIIb—XVIIIb in FIG.
18
(
a
); and FIG.
18
(
c
) is a bottom view thereof.
As shown in FIGS.
18
(
a
) through
18
(
c
), the conventional power QFN package includes a leadframe consisting of: signal leads
101
; a die pad
102
; and support leads
103
for supporting the die pad
102
. A semiconductor chip
104
with a built-in power electronic device is bonded on the die pad
102
with an adhesive
108
, and electrode pads (not shown) of the chip
104
are electrically connected to the signal leads
101
with metal fine wires
105
. And the die pad
102
except for its backside, semiconductor chip
104
, signal leads
101
, support leads
103
and metal fine wires
105
are molded with a resin encapsulant
106
. In this structure, no resin encapsulant
106
exists on the backside of the signal leads
101
. In other words, the backside of the signal leads
101
is exposed and the respective lower parts of the signal leads
101
, including the exposed back surfaces thereof, are used as external electrodes
101
a.
The backside
102
a
of the die pad
102
is not covered with the resin encapsulant
106
either, but functions as an exposed heat-radiating plate. By bringing this die pad
102
into contact with a heat-radiating portion of a motherboard, a heat quantity, which has been emitted from the power electronic device consuming a lot of power, can be dissipated, thus suppressing a rise in temperature within the package.
According to the conventional technique, when the power QFN package is mounted on a motherboard such as a printed wiring board, solder ball electrodes are attached onto the external electrodes
101
a
to ensure a standoff height as measured from the backside of the resin encapsulant
106
. This is done because the standoff height is required in bonding the external electrodes
101
a
, i.e., the lower parts of the signal leads
101
, to the electrodes of the motherboard. After the standoff height has been ensured by providing these ball electrodes in this manner, the package is mounted on the motherboard.
A power QFN package like this may be manufactured by performing the following process steps, for example. First, a leadframe, including the signal leads
101
, die pad
102
, support leads
103
and so on, is prepared. It should be noted that the leadframe prepared is often provided with dam bars for preventing the overflow of a resin encapsulant during resin molding. Next, the semiconductor chip
104
is bonded, with the adhesive
108
, onto the die pad
102
of the leadframe prepared. This process step is called “die bonding”. Then, the semiconductor chip
104
, which has been bonded onto the die pad
102
, is electrically connected to the signal leads
101
with the metal fine wires
105
. This process step is called “wire bonding”. As the metal fine wires
105
, aluminum (Al) or gold (Au) fine wires may be appropriately used, for example.
Subsequently, the semiconductor chip
104
, part of the die pad
102
except for the backside thereof, signal leads
101
, support leads
103
and metal fine wires
105
are molded with the resin encapsulant
106
such as an epoxy resin. In this case, the leadframe, on which the semiconductor chip
104
has been bonded, is introduced into a molding die assembly and transfer-molded. In particular, resin molding is performed with the backside of the signal leads
101
in contact with the upper or lower die of the die assembly. Finally, the ends of the signal leads
101
, protruding outward from the resin encapsulant
106
, are cut off after the resin molding process step. By performing this cutting process step, the end faces of the signal leads
101
cut off are substantially flush with the side faces of the resin encapsulant
106
. That is to say, this structure does not include any outer leads, which are ordinarily provided as external terminals. Instead, solder ball electrodes are provided for this structure as alternative external terminals under the external electrodes
101
a
, which are respective exposed lower parts of the signal leads
101
not covered with the resin encapsulant
106
. As the case may be, a solder plating layer is sometimes formed in place of the solder balls.
The conventional power QFN package, however, has the following drawbacks. First, since the lower surfaces of the external electrodes
101
a
are located in substantially the same plane as the resin encapsulant
106
on the backside of the semiconductor device, no standoff height is ensured as measured from the bottom of the resin encapsulant
106
. Thus, the device must be mounted onto a motherboard with the solder ball electrodes interposed therebetween. Accordingly, mounting cannot be carried out efficiently.
In the conventional manufacturing process of a resin-molded semiconductor device, a leadframe, on which a semiconductor chip has been bonded, is introduced into a die assembly. Then, the leadframe with the chip mounted is molded with a resin by pressing the signal leads against the surface of the lower die such that the leads come into close contact with the die. Even so, there occurs a problem that the resin encapsulant reaches the backside of the signal leads to form a resin burr (overflowed resin) on the surface of the external electrodes.
Thus, according to a proposed technique, a seal tape is interposed between the lower surface of the outer rail or the signal leads and the surface of the die assembly and resin molding is carried out with the lower parts of the signal leads forced into the seal tape. In this manner, those lower parts of the signal leads are protruded downward out of the resin encapsulant. In such a case, however, if the outer rail is deformed due to the clamping force applied to the outer rail and to the signal leads neighboring the outer rail, the force causing that deformation might be transmitted to the die pad by way of the support leads. As a result, the die pad might be deformed or displaced. It is imaginable to eliminate the support leads to obviate such inconvenience. Nevertheless, the reliability of the package might be risked because the die pad could not be supported with certainty in such a case.
In view of these respects, part of a suppo
Ito Fumito
Matsuo Takahiro
Minamio Masanori
Takemura Kunikazu
Yamada Yuichiro
Matsushita Electronics Corporation
Nixon & Peabody LLP
Robinson Eric J.
Williams Alexander O.
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