Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-10-07
2004-03-02
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S666000, C257S667000, C257S670000
Reexamination Certificate
active
06700192
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a leadframe used as a base frame of packages for mounting semiconductor elements. More specifically, the present invention relates to a leadframe which is used in a leadless package (a surface mounting semiconductor device) such as a quad flat non-leaded package (QFN) and has a lead shape suitable for solving a problem attributable to “burrs” occurring upon dicing in an assembly process of the package, and to a method of manufacturing a semiconductor device using the leadframe.
(b) Description of the Related Art
FIG. 1A
to
FIG. 1C
schematically show a constitution of a prior art leadframe for use in a leadless package such as QFN. In the drawings,
FIG. 1A
shows a plan-view constitution of a portion of the leadframe,
FIG. 1B
shows a cross-sectional structure of the leadframe viewed along A-A′ line in
FIG. 1A
, and
FIG. 1C
shows a cross-sectional structure of the leadframe viewed along B-B′ line in
FIG. 1A
, respectively.
In
FIG. 1A
to
FIG. 1C
, reference numeral
10
denotes a leadframe used as a substrate of the QFN. The leadframe
10
is basically composed of a base frame
11
obtained by patterning a metal plate such as a copper (Cu) plate. The leadframe
10
is formed such that die-pad portions
12
and lead portions
13
around the die-pad portions
12
are demarcated for respective semiconductor elements to be mounted thereon. Moreover, reference numeral
14
denotes frame portions. The respective lead portions
13
extend from the frame portions
14
toward the die-pad portions
12
in a comb shape. Also, each of the die-pad portions
12
is supported by four support bars
15
extending from four corners of the frame portion
14
.
Also, a metal film
16
is formed on the entire surface of the base frame
11
, and an adhesive tape
17
is adhered to a back surface (a lower plane in the illustrated example) of the base frame
11
. Adhesion (taping) of the adhesive tape
17
is basically performed as a countermeasure for preventing a leakage (which is also referred to as “mold flush”) of molding resin to the back surface of the frame upon molding in a package assembly process to be carried out at a later stage.
Also, reference symbol w
1
denotes a lead width of each lead portion
13
, and reference symbol d
1
denotes an interval (a lead interval) between two adjacent lead portions
13
. The respective lead portions
13
extend from the frame portions
14
in a comb shape with a constant lead width w
1
(FIG.
1
A). Moreover, broken lines CL show dividing lines for dividing the leadframe ultimately into respective packages in the package assembly process to be carried out at a later stage.
When a package (a semiconductor device) is assembled using the leadframe
10
having the above-described constitution, the basic process thereof includes the steps of mounting semiconductor elements on the die-pad portions of the leadframe (die bonding), electrically connecting electrodes of the semiconductor elements to the lead portions of the leadframe with bonding wires (wire bonding), sealing the semiconductor elements, the bonding wires and the like with molding resin (molding), dividing the leadframe into packages (semiconductor devices) after peeling off the adhesive tape (dicing), and the like. Also, as the type of molding, there are an individual molding in which the semiconductor elements are individually sealed with resin, and a mass molding in which the semiconductor elements are sealed together with resin. Since the individual molding has a difficulty in terms of efficient package assembly as compared to the mass molding, the mass molding has been a mainstream in recent years.
FIG.
2
A and
FIG. 2B
schematically show a constitution of a semiconductor device fabricated using the above-described leadframe
10
. In the drawings,
FIG. 2A
shows a cross-sectional structure of the semiconductor device viewed along A-A′ line in
FIG. 1A
, and
FIG. 2B
shows a cross-sectional structure of the semiconductor device viewed along B-B′ line in
FIG. 1A
, respectively.
In a semiconductor device
20
as exemplified in
FIG. 2A
, reference numeral
21
denotes a semiconductor element mounted on the die-pad portion
12
; reference numeral
22
denotes bonding wires electrically connecting respective electrodes of the semiconductor element
21
to the respective lead portions
13
; and reference numeral
23
denotes molding resin for protecting the semiconductor element
21
, the bonding wires
22
and the like. Also, reference symbol BR denotes “burrs” of metal generated from the lead portions
13
. Such burrs BR are generated on downstream sides of the cutting directions in the event of simultaneously cutting the metal (the lead portions
13
) and the resin (the molding resin
23
) along the dividing lines CL (
FIG. 1A
) with a dicer or the like in the dicing step of the above-described package assembly process.
In the assembly process of the packages (the semiconductor devices) such as QFN utilizing the mass molding, the burrs BR tend to be generated from the lead portions
13
as described above in the event of dicing the leadframe into the packages.
Where the burrs BR are generated, the adjacent lead portions
13
may be electrically short-circuited as exemplified in FIG.
2
B. As a result, there arises a disadvantage in that a productivity or a yield falls off, whereby a reliability of the packages (the semiconductor devices) as end products is degraded.
One of conceivable countermeasures for such a disadvantage is to widen the interval (the lead interval d
1
) between the adjacent lead portions
13
. However, the lead interval d
1
is selected to a specific value in an allowable range determined by a relationship between the size of the package and the number of external terminals required for the package. Accordingly, there is a limitation in the approach to widen the lead interval d
1
.
Meanwhile, the present inventors have carried out a series of experiments by means of varying roughness of a blade of a dicer and varying processing speed upon dicing. As a result, it has proved that generation of the burrs becomes more significant as the blade of the dicer is made relatively finer and the processing speed is controlled relatively slower.
For this reason, optimum conditions (the most appropriate roughness of the blade and the processing speed) for minimizing generation of the burrs are sought for each combination of a material of the metal and a material of the resin, and the dicing process is carried out based on the conditions. As a result, a complicated process is required for manufacturing a semiconductor device with fewer burrs. Eventually, there is a problem of an increase in cost in association therewith.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a leadframe and a method of manufacturing a semiconductor device using the leadframe, in which the leadframe is capable of effectively preventing a short circuit between adjacent lead portions even if burrs are generated upon dicing in an assembly process of the semiconductor device, thereby capable of enhancing a reliability of the semiconductor device, and also capable of contributing to shortening its manufacturing period and to decreasing its manufacturing cost.
To attain the above object, according to one aspect of the present invention, there is provided a leadframe including a die-pad portion disposed in a center of an opening defined by a frame portion; a plurality of lead portions extending from the frame portion toward the die-pad portion in a comb shape; and a lead width of a portion along a circumference of a region to be ultimately divided as a semiconductor device, of each of the lead portions, being formed narrower than a lead width of the other portion of the corresponding lead portion.
According to the leadframe of this aspect, the lead width of the portion to be detached from the frame portion (namely, the portion along the circumference of the region to be
Hayashi Shintaro
Matsuzawa Hideki
Clark Jasmine
Shinko Electric Industries Co. Ltd.
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