Lead on chip package

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Patent

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Details

257672, 257739, 257783, H01L 2156

Patent

active

057420963

ABSTRACT:
A lead on chip package comprising a semiconductor chip having a plurality of bonding pads and a plurality of minute protrusions formed at both side portions of the upper surface thereof, an insulating film made of a fluoroethylene film having knurled surfaces, and a plurality of inner leads each directly connected to each corresponding bonding pad of the semiconductor chip and provided with knurled surfaces. The formation of minute protrusions is accomplished by using a radio frequency (RF)-sputtering process at a low temperature. The formation of the knurled surfaces at the inner leads can be accomplished by passing the inner leads between rollers each having a knurled outer surface or by coating a nodule or dendrite layer over the surfaces of inner leads by an electro-plating using a high current density. Using the fluoroethylene film, the insulating film can reduce in thickness. By virtue of the knurled surfaces formed at the inner leads and the insulating film, the adhesion can be improved. It is also possible to prevent an occurrence of parasitic capacitance. As a result, there is provided an effect of assisting packages to be laminate.

REFERENCES:
patent: 4003073 (1977-01-01), Helda et al.
patent: 4151543 (1979-04-01), Hayakawa et al.
patent: 5086018 (1992-02-01), Conry et al.

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