Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-02-27
2003-09-09
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S615000
Reexamination Certificate
active
06617237
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS This application claims the priority benefit of Taiwan application serial No. 91103532, filed Feb. 27, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a bump fabrication process. More particularly, the present invention relates to a process for fabricating lead-free bumps over a wafer.
2. Description of Related Art
In the fabrication of integrated circuit packages, a chip is linked to a carrier inside a first level package in one of three ways including wire bonding, tape automatic bonding (TAB) and flip chip (F/C). In a tape automatic bonding or a flip chip package, the process of linking up the chip and the carrier involves the production of bumps on the bonding pads of the chip. In fact, the bump serves as an electrical medium for connecting the chip and the carrier. A variety of types of bumps have been developed such as solder bumps, gold bumps, conductive polymer bumps and polymer bumps. However, solder bumps are the most popular type.
A conventional method of fabricating a solder bump involves forming an under-ball-metallurgy (UBM) layer over the bonding pad of a wafer by evaporation, sputtering or electroplating. Thereafter, a thick photoresist layer is formed over the wafer. Through a plurality of openings that exposes the under-ball-metallurgy layer, solder material is deposited into the opening by evaporation, electroplating or printing. Finally, a reflow process is conducted fusing the solder material together to form a solder bump having a spherical external appearance.
Lead-tin alloy (Sn-Pb alloy) is a material having ideal physical and conductive properties for forming solder bump aside from forming connections between devices or circuit boards. However, lead is an environmentally hazardous material that may affect the health of people. Hence, the electronic industry has been actively searching for lead-free solder alloy material to replace conventional lead-tin alloy material.
Most lead-free alloy contains tin and (one or more) other metallic elements. Common metallic elements other than tin to be used inside a lead-free alloy include gold (Au), silver (Ag), copper (Cu), magnesium (Mg), bismuth (Bi), antimony (Sb), indium (In) and zinc (Zn). Aside from lead-free solder alloy containing tin, lead-free solder alloy may contain no tin. In other words, lead-free solder alloy also includes solder material that has no traces of tin. Similarly, a lead-free solder refers to a solder material containing no traces of lead only and may or may not contain any tin. In a conventional lead-free solder bump fabrication process, metallic elements in a specified ratio are used to produce an alloy of lead-free solder material. This lead-free solder material is deposited over a wafer and then a reflow process is carried out to form a lead-free solder bump.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a lead-free solder bump fabrication process that includes forming a lead-free pre-formed solder bump over a wafer, depositing solder material on the lead-free solder bump and conducting a reflow process to form a lead-free solder bump. Since the lead-free pre-formed solder bump and the lead-free solder material may contain different constituents and may be composed of a single metal or an alloy of metals, ultimate composition of the lead-free solder bump can be easily adjusted.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a lead-free solder bump fabrication process for forming a plurality of lead-free solder bumps over a wafer. The wafer has an active surface with a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads. First, an under-ball-metallurgy layer is formed over the bonding pads. A lead-free pre-formed solder bump is formed over each under-ball-metallurgy layer. Thereafter, a patterned solder mask is formed over the active surface of the wafer. The solder mask layer has a plurality of openings that exposes the respective lead-free pre-formed solder bumps. A lead-free solder material is deposited into the openings. The lead-free solder material may contain constituents that differ from the lead-free pre-formed solder bump. A reflow process is conducted so that the lead-free pre-formed solder bump and the lead-free solder material may fuse together to produce a lead-free solder bump. Finally, the solder mask layer is removed.
The lead-free solder bump fabrication process according to this invention includes forming an under-ball-metallurgy layer over the bonding pads of a wafer and forming a lead-free pre-formed solder bump over the under-ball-metallurgy layers. Thereafter, a patterned solder mask layer having a plurality of openings that exposes the lead-free pre-formed solder bumps is formed over the wafer. Lead-free solder material is deposited into the openings stacking on top of the lead-free pre-formed solder bump. A reflow process is carried out so that the lead-free pre-formed solder bump and the lead-free solder material are fused together to produce a lead-free solder bump. Finally, the solder mask layer is removed. Because the lead-free pre-formed solder bump and the lead-free solder material may be fabricated using different constituents, composition of the lead-free solder bump can be easily adjusted.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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patent: 6281581 (2001-08-01), Desai et al.
patent: 6380060 (2002-04-01), Zohni
patent: 6413851 (2002-07-01), Chow et al.
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Joshi et al., US patent application Publication 2002/0192935A1, Dec. 2002.
Chen Jau-Shoung
Chou Yu-Chen
Fang Jen-Kuang
Huang Min-Lung
Lee Chun-Chi
Advanced Semiconductor Engineering Inc.
Jiang Chyun IP Office
Nguyen Ha Tran
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