Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
1999-08-12
2001-08-21
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S713000, C257S717000, C257S667000, C257S774000, C257S780000
Reexamination Certificate
active
06278182
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88100105, filed Jan. 6, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor package structure. More particularly, the present invention relates to a semiconductor package with a higher cooling capability.
2. Description of Related Art
As the integration of an integrated circuit (IC) chip increases, capability and pin count of the IC package also increase correspondingly. In the meantime, the package is more vulnerable to interference by external electromagnetic fields and damages caused by high temperature. Due to an increase in the level of integration, overall volume of an IC package decreases or remains the same despite an increase in pin count. However, a larger pin count for the same package volume means that the pin-to-pin separation has to decrease, and a decrease in pin-to-pin separation renders IC chip packaging more difficult. To resolve the issue, a ball grid array (BGA) type of package structure has been developed. Furthermore, heat generated by the IC chip can be dissipated and unwanted electromagnetic fields can be shielded by including a heat sink in the package.
FIG. 1
is a schematic, cross-sectional view of a conventional BGA package. As shown in
FIG. 1
, a silicon chip
12
is mounted on a lead frame
10
and is electrically connected to the leads of the lead frame by conductive wires
14
. There is a heat sink
16
arching over the lead frame
10
, as well. Besides increasing the cooling of the silicon chip
12
, the heat sink
16
is also capable of shielding the chip
12
against interference from external electromagnetic fields. The lead frame
10
, the silicon chip
12
, the conductive wires
14
and a portion of the heat sink
16
are enclosed by placing the lead frame
10
into a mold (not shown) after which a packaging material
20
is injected into the mold. On solidification, the packaging material
20
not only fixes the positions various internal elements, but also provides additional protection against vibration or impact. There is a metallic plate
13
at one corner of the lead frame
10
. The metallic plate
13
is located under a gate (not shown), which is an opening through which the packaging material enters the mold. By introducing a smooth metallic plate
13
under the gate, packaging material
20
is able to flow rapidly into the mold cavity. After molding, the mold is dissembled and the package is taken out. Any residual material remaining above the gate can be easily scratched away due to the presence of a smooth metallic surface under the gate.
However, the gate is located at one corner of the packaging cavity inside a mold. Because packaging material
20
has to traverse the cavity from the gate at one corner to the opposite corner, a longer period is needed to fill the entire packaging cavity. Besides slowing the molding process, the longer flow path through this gate arrangement may introduce additional pressure that can result in residual stress inside the package after setting. Furthermore, to secure the heat sink
16
, a large section of the heat sink
16
has to be enclosed by the packaging material
20
. Since only a portion of the heat sink
16
is exposed, capacity for cooling a silicon chip is greatly reduced.
In brief, the disadvantages of a conventional BGA package include:
1. Since packaging material is injected through a gate at one comer of the packaging cavity, a high amount of residual stress is likely to remain inside the package on solidification. In addition, a longer period is needed to fill the entire packaging cavity.
2. After molding, residual material on the gate has to be removed from the package, thereby incurring addition cost.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a semiconductor package structure that can be formed in fewer steps and has a higher quality.
A second object of the invention is to provide a semiconductor package having a higher cooling capacity and a more effective electromagnetic shield.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor package. The package includes a silicon chip, a lead frame for supporting the silicon chip and a plurality of conductive wires that connects the silicon chip with leads on the lead frame. There is a heat sink above the silicon chip. The heat sink has a pinhole gate and a plurality of positioning holes. The pinhole gate is a narrow tubular pipeline. The positioning holes are conical cavities whose bigger diameter is away from the chip. In addition, the pinhole gate and the positioning holes on the heat sink are filled by packaging material during the process. The packaging material also encloses the silicon chip, the conductive wires and a portion of the heat sink. The packaging material is able to fix the positions of the silicon chip, the conductive wires and the heat sink relative to each other.
Furthermore, the pinhole gate is located in the middle of the roof of the packaging cavity. Hence, when packaging material is injected into the packaging cavity, a uniform pressure is created inside the cavity. Moreover, a three-piece mold is used. Therefore, when the mold is dissembled, residual packaging material breaks at the junction between the pinhole gate and the mold gate. Hence, there is no need to remove residual material in a separate step. Moreover, the conical holes on the heat sink are able to position the heat sink when packaging material inside the holes solidifies.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5105259 (1992-04-01), McShane et al.
patent: 5835355 (1998-11-01), Dordi
patent: 5977633 (1999-11-01), Suzuki et al.
patent: 6046499 (2000-04-01), Yano et al.
Lai Chien-Hung
Liu Wen-Chun
Fenty Jesse A.
Huang Jiawei
J.C. Patents
Lee Eddie
Walsin Advanced Electronics Ltd.
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