Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2005-03-15
2005-03-15
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S669000, C257S671000, C257S672000, C257S674000, C257S696000, C257S698000, C257S730000, C257S712000, C257S713000
Reexamination Certificate
active
06867481
ABSTRACT:
A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.
REFERENCES:
patent: 4942452 (1990-07-01), Kitano et al.
patent: 4942454 (1990-07-01), Mori et al.
patent: 5105259 (1992-04-01), McShane et al.
patent: 5397915 (1995-03-01), Nose
patent: 5637913 (1997-06-01), Kajihara et al.
patent: 5637916 (1997-06-01), Joshi
patent: 5659199 (1997-08-01), Mori et al.
patent: 5765280 (1998-06-01), Joshi
patent: 5789809 (1998-08-01), Joshi
patent: 5874773 (1999-02-01), Terada et al.
patent: 5920116 (1999-07-01), Umehara et al.
patent: 6133634 (2000-10-01), Joshi
patent: 6191490 (2001-02-01), Huang
patent: 6294403 (2001-09-01), Joshi
patent: 6329706 (2001-12-01), Nam
patent: RE37690 (2002-05-01), Kitano et al.
patent: 6469384 (2002-10-01), Joshi
patent: 6489678 (2002-12-01), Joshi
patent: 6566749 (2003-05-01), Joshi et al.
patent: 6624522 (2003-09-01), Standing et al.
patent: 20010007780 (2001-07-01), Minamio et al.
patent: 20010054640 (2001-12-01), Takahashi
patent: 20020065661 (2002-05-01), Everhart et al.
patent: 20020066950 (2002-06-01), Joshi
patent: 20020066959 (2002-06-01), Joshi
patent: 20020100962 (2002-08-01), Joshi
patent: 20020192935 (2002-12-01), Joshi et al.
patent: 20030001244 (2003-01-01), Araki et al.
patent: 20030011005 (2003-01-01), Joshi
patent: 20030042403 (2003-03-01), Joshi
patent: 20030075786 (2003-04-01), Joshi et al.
patent: 20030107126 (2003-06-01), Joshi
patent: 20030122247 (2003-07-01), Joshi
patent: 20030234446 (2003-12-01), Diot et al.
patent: 20040063240 (2004-04-01), Madrid et al.
patent: 20040104489 (2004-06-01), Larking
patent: 6-21317 (1994-01-01), None
U.S. Appl. No. 10/413,668, filed Apr. 13, 2003, Cabahug et al.
“Test Method A105-B: Power and Temperature Cycling, EIA/JESD 22-A105-B,”EIA/JEDEC Standard, Electronic Industries Association, (Feb. 1996).
“Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing, JESD22-A113-B,”EIA/JEDEC Standard, Electronic Industries Association, (Mar. 1999).
“Temperature Cycling, JESD22-A104-B,”JEDEC Standard, JEDEC Solid State Technology Association, (Jul. 2000).
“Accelerated Moisture Resistance—Unbiased Autoclave, JESD22-A102-C”,JEDEC Standard, JEDEC Solid State Technology Association, (Dec. 2000).
Joshi Rajeev
Wu Chung-Lin
Fairchild Semiconductor Corporation
Williams Alexander Oscar
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