Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2007-08-21
2007-08-21
Le, Thao P. (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S111000, C438S106000, C257S666000, C257S673000
Reexamination Certificate
active
11020036
ABSTRACT:
In a method of manufacturing a lead frame for use in a leadless package such as a quad flat non-leaded package (QFN), a base frame is first formed which includes a region for resin-molding a plurality of semiconductor elements to be mounted on one surface of the base frame, the region being partitioned into land shapes, and in which a die-pad portion and lead portions around the die-pad portion are defined severally for the individual semiconductor elements to be mounted in each of the partitioned regions for resin-molding. Next, an adhesive tape is attached to the other surface of the base frame, and subsequently a cut portion is provided at a portion corresponding to a region between two adjacent partitioned regions for resin-molding, of the adhesive tape.
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Japanese Patent Office Action for corresponding Japanese Patent Application No. 2001-328528 dated Mar. 29, 2005 with partial translation.
Kasahara Tetsuichiro
Tanaka Hideto
Kratz Quintos & Hanson, LLP
Le Thao P.
Shinko Electric Industries Co. Ltd.
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