Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – Small lead frame for connecting a large lead frame to a...
Reexamination Certificate
1999-11-09
2003-03-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
Small lead frame for connecting a large lead frame to a...
C257S666000, C257S667000, C257S670000, C438S111000, C438S112000, 43, 43
Reexamination Certificate
active
06534846
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a lead frame for a semiconductor device and a semiconductor device using the same.
2. Description of the Related Art
A lead frame is a member used to make a resin encapsulation package, which encapsulates a semiconductor chip and is mounted on a substrate, such as a printed circuit board, to electrically connect the semiconductor chip to the substrate. An example of such a lead frame is shown in
FIG. 1
, which is applied for manufacture of package for a lead on chip (LOC) type.
A lead frame
100
shown in
FIG. 1
comprises, in general, inner leads
104
, outer leads
106
, and dam bars
108
. The inner lead
104
has a first end
104
a
, which is connected to an electrode pad
102
of a semiconductor chip
101
, and a second end
104
b
, which is connected to the outer lead
106
, and is ultimately encapsulated by a resin to form a package
103
. The outer lead
106
serves as a terminal for electrically connecting the package
103
to an external circuit. The dam bar
108
connects adjacent outer leads
106
to each other and dams up an encapsulating resin material during the preparation of the package
103
, and is cut away prior to practical use of the package
103
. Although this drawing shows only a portion of each outer lead
106
near the dam bar
108
, the respective outer leads
106
, in fact, extend outwardly and have equal lengths. For simplicity, the drawing shows the semiconductor chip
101
and the package
103
by phantom lines, and omits most of inner leads
104
and all of connections between the first ends
104
a
of the inner lead
104
and the electrode pads
102
of the chip
101
.
The electrode pads
102
of the semiconductor chip
101
line up in.a long and narrow region A to form an array. The first ends
104
a
of the inner leads
104
are located along both sides of the region A, at a certain pitch P
1
, to be connected to the respective electrode pads
102
by, for example, a wire (not shown). Thus, the first ends
104
a
of the inner leads
104
are arranged in two arrays. These arrays of first ends
104
a
of the inner leads
104
are in parallel with each other and with the array of the electrode pads
102
of the chip
101
. Each inner lead
104
has a second end
104
b
to be connected to the outer lead
106
, and the ends
104
b
of the respective inner leads
104
are located at opposed sides of the lead frame
100
to form arrays, which are in parallel with each other and with the arrays of the first ends
104
a
of the inner leads
104
and the electrode pads
102
of the chip
101
, and have a certain pitch P
2
broader than pitch P
1
of the arrays of first ends
104
a.
As described above, the first ends
104
a
of the inner lead
104
are arranged into two arrays B, and the second ends
104
b
of the inner lead
104
are arranged into two arrays C. These four arrays are in parallel with the longitudinal center line D of the array of the electrode pads
102
of the chip
101
, with the two arrays B being symmetrical with regard to the center line D, and the two arrays C also being symmetrical with regard to the center line D. In addition, the respective centers of the four arrays are located on the line E which crosses the center O of the array of the electrode pads
102
and is perpendicular to the center line D of the array of the electrode pads
102
. Thus, the arrays B of the first ends
104
a
are symmetrical with regard to the center O, and the arrays C of the second ends
104
b
are also symmetrical with regard to the center O.
It is conventional that the intermediate portion connecting the first end
104
a
to the second-end
104
b
of each inner lead
104
is formed in a straight line so as to link the electrode pad
102
to the outer lead
106
over the shortest distance. Accordingly, the inner lead
104
adjacent to the line E has a smallest length, the inner lead
104
farthest from the line E has a largest length, and the inner leads
104
between them having a length which is intermediate between both lengths, with the farther, the longer. Thus, the inner leads
104
have uneven lengths.
Recently, as the clock frequency of a central processing unit (CPU) increasingly becomes higher, packages for semiconductor devices used in CPUs and associated large scale integrated circuits (LSIs) are required to cope with such a higher frequency. For this purpose, it is envisaged, for example, (1) to use shorter signal lines for less delay time, (2) to use a transmitting line structure of signal lines having an equivalent characteristic impedance, or (3) to use signal lines of equivalent lengths to eliminate or reduce variation of delay times between the signal lines. As a technique to specifically realize such requirements, reference can be made to use of chip sized package (CSP).
Nevertheless, in the case of CSPs, a package has matrix-like terminals for external connection of, for example, 0.75 millimeter pitch, which raises a problem of a higher cost because of a necessity of substrate allowing a package or packages having terminals in such a higher density to be mounted thereon. In addition, CSPs have not yet demonstrated sufficient reliability for mounting on a substrate.
SUMMARY OF THE INVENTION
The invention relates to semiconductor devices using a lead frame, which have been, unlike CSPs, successfully used, to date, in large quantities. Thus, it is an object of the invention to provide a lead frame enabling a semiconductor chip operating at a higher frequency to be mounted thereon. The invention further provides a semiconductor device using such a lead frame, and a method of producing the lead frame.
In one aspect, the invention provides a lead frame for semiconductor device comprising inner leads for electrical connection with a semiconductor chip, outer leads linked with the respective inner leads and used for electrical connection with a substrate on which the semiconductor device is mounted, and dam bars linking the adjacent outer leads together and preventing an encapsulating material from intruding into between the outer leads during encapsulation of the semiconductor chip together with the lead frame to produce the semiconductor device, the inner leads being divided into two groups which are located in opposed areas of the lead frame divided by the center line of the array of the electrode pads of the semiconductor chip, and the inner lead having a first end and a second end, the first ends of the respective inner leads, for the electrical connection with the semiconductor chip, being arranged into arrays along an array of electrode pads of the semiconductor chip, so that the array of the first ends has a pitch corresponding to a pitch in the array of the electrode pads, the second ends of the respective inner leads for the linkage with the outer leads being arranged into arrays at opposed sides of the lead frame, so as to have a pitch larger than the pitch in the array of the first ends, wherein at least some of the inner leads are arranged so as to have lengths between the first and the second ends which are substantially equivalent to each other.
Preferably, in each of the opposed areas, the centers of the arrays of the first and the second ends of the inner leads are displaced from each other in the direction of the arrays.
Preferably, in each of the opposed areas, the array of the first ends of the inner leads is positioned in one of two sections divided by the line crossing the center of the array of the electrode pads of the chip perpendicularly to the array of the electrode pads, and the array of the second ends of the inner leads is positioned in the other of the two sections.
Preferably, a set of the inner leads in the one of the two areas and a set of the inner leads in the other of the two areas are positioned symmetrically with regard to the center of the array of the electrode pads.
Preferably, said some of the inner leads, arranged so as to have lengths between the first and the second ends which are substantially equivalent to
Chu Chris C.
Lee Eddie
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
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