Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2002-12-13
2004-01-13
Clark, Sheila V. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S666000, C257S707000
Reexamination Certificate
active
06677666
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a surface mount type semiconductor device and a lead frame used for fabricating the same. More particularly, the present invention relates to downsizing a surface mount type semiconductor device without deteriorating reliability thereof and to realizing a lead frame suitable for such downsizing.
BACKGROUND OF THE INVENTION
Portable type electronic circuit apparatuses such as a video camera, a notebook type personal computer and the like are being urged to be small in size and light in weight. Thus, it is strongly desired that electronic parts used in these electronic circuit apparatuses such as semiconductor devices and the like are also downsized and thinned. In order to cope with such requirements, electronic parts themselves are downsized. Alternatively, even if the external size of each of the electronic parts is the same or slightly larger than before, electronic elements therein are more highly integrated and, thereby, the electronic parts are made substantially small in size and light in weight.
FIG. 14
is a partial perspective view illustrating a conventional lead frame used for fabricating a semiconductor device. The lead frame
105
shown in
FIG. 14
is used for fabricating a power semiconductor device which emits much heat when operated.
The lead frame
105
shown in
FIG. 14
comprises a pair of band shaped members, that is, first and second band shaped members
101
and
102
disposed parallel to each other. The width of the first band shaped member
101
is smaller than that of the second band shaped member
102
. In the second band shaped member
102
, holes or perforations
102
a
for transferring the lead frame
105
are formed at intervals of a predetermined constant length. The lead frame
105
further comprises island portions or heat sinks
103
, and leads
104
. The heat sinks
103
are disposed outside the first band shaped member
101
, that is, on the opposite side of the second band shaped member
102
, with predetermined spaces therebetween. The leads
104
comprise lead sets each of which has mutually parallel three leads
104
a
,
104
b
and
104
c
. A large number of lead sets of the leads
104
extend from an edge portion of the second band shaped member
102
beyond the first band shaped member
101
. Therefore, the first band shaped member
101
is coupled with the second band shaped member
102
via the leads
104
. In each lead set of the leads
104
, the center lead
104
a
is coupled, at an edge portion thereof, with an edge portion of the heat sink
103
. End portions of other leads in each lead set are not coupled with the heat sink, but are located near the edge portion of the heat sink
103
.
With reference to the drawings, an explanation will be made on a method of manufacturing a conventional power semiconductor device.
FIG. 15
is a side cross sectional view of a conventional power semiconductor device fabricated by using the lead frame
105
shown in
FIG. 14
, and
FIG. 16
is a top perspective view of the semiconductor device. For the sake of easy understanding,
FIG. 16
shows a structure of a portion within an encapsulation resin by using perspective representation.
First, a semiconductor pellet
107
is mounted on the heat sink
103
by using a solder
106
. Then, electrodes (not shown in the drawing) on the semiconductor pellet
107
and the leads
104
b
and
104
c
are electrically coupled via wires
108
a
and
108
b
, respectively. The wire
108
a
through which a main current flows is constituted of a thick wire. The main portion on the heat sink
103
including the semiconductor pellet
107
is coated with an encapsulation resin
109
. In this case, the back surface of the heat sink
103
is exposed from the encapsulation resin
109
. Also, as shown in
FIG. 16
, the lead
104
a
is disposed in a concave portion
109
a
of the encapsulation resin
109
. Therefore, the surface of the encapsulation resin
109
from which the lead
104
a
coupled with the heat sink
103
comes out is recessed from the surface of the encapsulation resin
109
from which other leads
104
b
and
104
c
come out. Thereby, creepage distances between the lead
104
a
and the leads
104
b
and between the lead
104
a
and
104
c
can be elongated, and it is possible to assure a safe operation of the semiconductor device at a high voltage.
After encapsulation by the encapsulation resin
109
is completed, unnecessary portions of the first and second band shaped members
101
and
102
of the lead frame
105
which connect the leads
104
are cut and removed. Thereby, the leads
104
are separated and the semiconductor device shown in
FIG. 16
is completed.
Also, the center lead
104
a
is cut within the concave portion
109
a
of the encapsulation resin
109
. Each of the leads
104
b
and
104
c
is bent into a crank shape near the encapsulation resin
109
. Thereby, end portions of the leads
104
b
and
104
c
are made coplanar with the exposed surface of the heat sink
103
.
FIG. 17
is a side cross sectional view showing a conventional surface mount type power semiconductor device which is manufactured in this way. In the semiconductor device shown in
FIG. 17
, it is possible to directly solder the heat sink
103
and the leads
104
b
and
104
c
to conductive islands of a wiring substrate not shown in the drawing. Therefore, it is possible to lower the height of the semiconductor device mounted on the wiring substrate. Semiconductor devices of this type are disclosed, for example, in Japanese utility model laid-open publication No. 62-188149, Japanese patent laid-open publication No. 4-340264, Japanese patent laid-open publication No. 5-283574 and the like.
In the above-mentioned conventional semiconductor device, it is possible to lower the height thereof. However, since the leads
104
b
and
104
c
protrude from the encapsulation resin
109
, it is impossible to sufficiently reduce the mounting area of the semiconductor device.
FIG. 18
is a side cross sectional view illustrating another conventional surface mount type power semiconductor device which can obviate the above-mentioned disadvantage.
FIG. 19
is a bottom view of the semiconductor device of FIG.
18
. In FIG.
18
and
FIG. 19
, like reference numerals are used to designate identical or corresponding parts to those of the conventional semiconductor device of
FIG. 17
, and detailed description thereof is omitted here. In the semiconductor device shown in
FIGS. 18 and 19
, portions of leads
104
b
and
104
c
near a heat sink
103
are made coplanar with a surface of the heat sink
103
. Also, at the bottom surface of the semiconductor device, portions of the leads
104
b
and
104
c
together with the heat sink
103
are exposed from an encapsulation resin
109
. Leads
104
a
,
104
b
and
104
c
coming out from the encapsulation resin
109
are cut in the proximity of the encapsulation resin
109
. By using this structure, it is possible to further downsize the semiconductor device.
In the semiconductor device having the structure shown in
FIG. 18
, the area of the heat sink
103
is made as large as possible so that good heat dissipating ability can be obtained. However, in this semiconductor device, it is necessary that the leads
104
b
and
104
c
are disposed apart from the lead
104
a
. Therefore, the areas of electrode portions of the leads
104
b
and
104
c
exposed from the encapsulation resin
109
at the bottom surface of the semiconductor device must be relatively small with respect to the exposed area of the heat sink
103
.
When the semiconductor device having this structure is soldered on conductive land portions of a wiring substrate, the semiconductor device floats on melted solders and becomes unstable. Therefore, there was a possibility that the semiconductor device rotates or moves from a predetermined mounting location of the semiconductor device.
Further, the heat sink
103
and the leads
104
b
and
104
c
are disposed coplanar with each other. Therefore, when the thickness
Kaneda Yoshiharu
Uchiyama Tokuhiro
Clark Sheila V.
NEC Electronics Corporation
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