Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
1998-02-23
2001-01-30
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
active
06181000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device having a lead frame, and more particularly to a lead frame for ball grid array, a semiconductor device having it, and a process for producing it.
2. Description of the Prior Art
Recent semiconductor devices need a higher degree of integration and more functions than before to meet requirements for electronic machines and equipment which are improving in performance and becoming light in weight and small in size. However, this need is not met by conventional QFP (Quad Flat Package) which becomes larger in size and whose external terminals become narrower in pitch as the number of lead frame pins increases. As the result, lead frames are more liable to deformation and defective mounting is liable to occur more frequently.
In order to eliminate this disadvantage, there has been developed the ball grid array (BGA) which uses external terminals with solder balls for the mounting of a semiconductor device.
The BGA enables the lead frame to have more widely pitched external terminals and hence it enables the number of external terminals to increase without adverse effect on the mounting of semiconductor devices.
The lead frame for BGA is usually constructed as shown in FIG.
4
. It is formed by etching or pressing. Like conventional QFP, it is designed such that a semiconductor chip is mounted on the die pad and the forward ends of the inner leads are connected by wire bonding to the terminals of the semiconductor element. It differs from QFP in that the terminals for mounting are ball bumps.
The conventional lead frame shown in
FIG. 4
suffers the disadvantage that the forward ends
2
of the inner leads with terminal ball bumps
1
have extremely narrow spaces because they are connected by wiring bonding to the semiconductor element. Producing such lead frames with high precision by etching or pressing is necessarily low in yields.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new lead frame for BGA which permits the number of pins to increase without adverse effect on its function, a semiconductor device having it, and a process for producing it in high yields.
The first aspect of the present invention resides in a lead frame for ball grid array which is composed of a plurality of inner leads extending from outside to inside and having terminal ball bumps formed somewhere along them, characterized in that the terminal ball bumps are formed in at least two rows, with adjacent ones not overlapping in the lengthwise direction of the inner lead and the rows holding the bonding area between them.
In the first aspect of the present invention, the bonding area should preferably be formed at the middle of the rows of the terminal ball bumps and at least the bonding area should preferably be plated with gold, silver, or palladium.
Moreover, in the first aspect of the present invention, the inner leads should preferably have their tips cut short and formed wide by patterning or coining with the corresponding width.
The second aspect of the present invention resides in a semiconductor device which comprises a semiconductor element mounted on a lead frame for ball grid array which is composed of a plurality of inner leads extending from outside to inside and having terminal ball bumps formed an alternately coinciding manner somewhere along them in at least two rows, with the rows holding the bonding area between them, the ball bumps having solder balls joined to them. The semiconductor element is mounted by means of an adhesive tape based on a thermoplastic resin adhesive or thermosetting resin adhesive.
The third aspect of the present invention resides in a process for producing a semiconductor device which comprises bonding a semiconductor element to an approximately central part of a lead frame for ball grid array with an adhesive layer interposed in-between, connecting by wire bonding the terminals of the semiconductor element to the boding area of the inner lead, performing molding with a molding resin, connecting solder balls to the terminal ball bumps, and removing unnecessary parts of the inner lead, the lead frame being composed of a plurality of inner leads extending from outside to inside and having terminal ball bumps formed an alternately coinciding manner somewhere along them in at least two rows, with said rows holding the bonding area between them, said ball bumps having solder balls joined to them. The adhesive tape is one which is based on a thermoplastic resin adhesive or thermosetting resin adhesive.
REFERENCES:
patent: 4685210 (1987-08-01), King et al.
patent: 5442230 (1995-08-01), Chillara et al.
patent: 5468999 (1995-11-01), Lin et al.
patent: 5522133 (1996-06-01), Kawauchi
patent: 5559366 (1996-09-01), Fogal et al.
patent: 5663593 (1997-09-01), Mostafazadeh et al.
patent: 5663594 (1997-09-01), Kimura
patent: 5767575 (1998-06-01), Lan et al.
patent: 5847455 (1998-12-01), Manteghi
Nakagawa Naoki
Ooigawa Kinya
Yoshida Tayuru
Dykema Gossett PLLC
Jr. Carl Whitehead
Sumitomo Metal & Mining Co., Ltd.
Vockrodt Jeff
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