Lead frame for an integrated circuit chip

Details Lead frame for an integrated circuit chip Lead frame for an integrated circuit chip

2000-02-07

2003-09-16

Cuneo, Kamand (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

C257S676000

Reexamination Certificate

active

06621151

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to packaging for a semiconductor device, and more particularly to a crack and delamination inhibiting lead frame for a semiconductor integrated circuit with a small window.
Conventional plastic semiconductor packages suffer from a failure mode referred to as “popcorn cracking.” This failure mode occurs in packages that are exposed to ambient moisture and are then heated to high temperatures, typically during reflow soldering.
The problem apparently arises because plastic IC packages have a tendency to absorb moisture from the environment. The moisture diffuses into the encapsulant material and other materials such as the chip attach. During the solder reflow process, thermal vapor stresses developed at the chip attach/chip-pad interface or the encapsulant material/chip-pad interface cause delamination to occur, especially at areas of high interfacial stress.
A conventional full pad design is shown in
FIGS. 6
,
6
A and
6
B where a chip or die
10
has its lower side
12
secured to a chip pad
14
by a chip attach material
16
. The chip attach
16
forms a fillet
18
between the side wall
20
of the chip
10
and the upper surface
22
of the chip pad
14
in an outer region known as the shoulder
24
. The pad
14
and attached chip
10
are thereafter encapsulated in an encapsulant material
26
, for example epoxy forming a package
30
in a known manner. In
FIG. 6A
, the package
30
is fabricated on a metal leadframe
31
. The package
30
includes wire bonds
37
.
The failure process appears to begin with delamination or cracking of the bond between the chip and the chip-pad. This delamination may be caused by differential expansion due to the differing coefficients of thermal expansion of adjacent materials within the package. Delamination
38
of the chip
10
from the chip pad
14
can occur when the interfacial stresses exceed the interfacial strength. Once delamination begins, it can propagate. The expanding void created by this delamination is invaded by water vapor, previously absorbed into the encapsulant material, and driven from the encapsulant by the rise in temperature. If the delamination covers a large area, the resulting long moment across which expansive water vapor forces act allows those forces to overcome the cohesive forces within the encapsulant material. In particular, delamination
38
often starts near the corner
32
of the chip
10
, where the chip
10
meets the shoulder
24
. In the case of the full pad design shown, delamination can rapidly propagate over the entire pad area. This can cause the package
30
to crack from the outer edge
34
of the chip pad
14
where the cohesive strength of the encapsulant material
26
is exceeded. The resulting crack may propagate through the encapsulant material
26
to the outer surface
36
of the package
30
. In a like manner, delamination of the chip pad
14
from the encapsulant material
26
can also act as a crack source resulting in a popcorn failure.
These problems necessitate storage of components in humidity controlled environments prior to reflow soldering. Such required storage procedures represent additional cost and uncertainty in product quality.
SUMMARY OF THE INVENTION
The invention is based upon the discovery that a lead frame for a crack resistant integrated circuit package has an apertured frame, of reduced size, smaller than the integrated circuit. In a package utilizing the lead frame, the integrated circuit or chip is attached to the upper surface of the frame, and encapsulant material encloses and surrounds the frame and the chip. The encapsulant material bonds to a majority of the surface area of the chip and hardens to complete the package.
The invention provides a lead frame that reduces the initial adhesive failure, or delamination, that can occur during high temperature exposure that results in popcorn cracking. In an exemplary embodiment, this is achieved by reducing or minimizing the size of the attachment surface of the frame to the chip. The minimal attachment surface limits the propagation of cracks and increases the available bonding surface area below the chip and encapsulant.


REFERENCES:
patent: 4884124 (1989-11-01), Mori et al.
patent: 4924291 (1990-05-01), Lesk et al.
patent: 4942452 (1990-07-01), Kitano et al.
patent: 5150193 (1992-09-01), Yasuhara et al.
patent: 5233222 (1993-08-01), Djennas et al.
patent: 5352852 (1994-10-01), Chun
patent: 5543657 (1996-08-01), Diffenderfer et al.
patent: 5637913 (1997-06-01), Kajihara et al.
patent: 5661338 (1997-08-01), Yoo et al.
patent: 5874773 (1999-02-01), Terada et al.
patent: 6087715 (2000-07-01), Sawada et al.
patent: 6091133 (2000-07-01), Corisis et al.
patent: 6130115 (2000-10-01), Okumura et al.
patent: 6137160 (2000-10-01), Ishikawa
patent: 6166430 (2000-12-01), Yamaguchi
Umehara, Norito et al., S-Pad Implementation; Total Plastic Package Crack Solution for Non-Moisture Sensitive Pakcage, New Package Development, Texas Instruments Japan, Ltd., Hi j. i. Plant, 4260 takao, Kawasaki, Hiji-machi, Hayami-gun Oita Japan 879-15.
Ganesan, Gans S. et al., Level I CrackFree Plastic Packaging Technology, Motorola Inc., Semiconductor Products Sector, 2100 E. Elliot Road, Tempe, AZ 85284.
Nakazawa, Tsutomu et al., A Novel Structure to Realize Crack-Free Plastic Packages During Reflow Soldering Process-Development of Chip Side Support (CSS) Package, IEEE Transactions on Components Packaging and Manufacturing Technology—Pact C, vol. 19, No. 1, Jan. 1996, pp. 61-69.
Chan, K. C. and Chai, T. C., Type II Popcorn Failure Analysis in Plastic Encapsulated IC Package Using Scanning Acoustic Microscopy and Cross-Sectioning (not yet published).
Cha, Ki-Bon et al.; Ultra-Thin and Crack-Free Bottom Leaded Plastic (BLP) Package Design; LG Semicon (Gold Star) Package R&D Center, Cheongju, Korea 360-480 0569-5503/95/0000 ©1995 IEEE.

Affiliated with

Also associated with

Rating

Lead frame for an integrated circuit chip does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Lead frame for an integrated circuit chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lead frame for an integrated circuit chip will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3088141