Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – Small lead frame for connecting a large lead frame to a...
Reexamination Certificate
2001-12-17
2004-03-02
Pert, Evan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
Small lead frame for connecting a large lead frame to a...
C257S674000, C257S675000, C257S676000, C257S670000, C257S666000, C257S796000, C257S692000, C438S106000, C438S123000
Reexamination Certificate
active
06700186
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices each incorporating a unit lead frame made as by performing a mold array process (MAP). The invention is also directed to a method of making a semiconductor device.
2. Background Art
It is known to make semiconductor devices by bonding semiconductor chips to a lead frame and applying a sealing resin over the chip at one side of the unit lead frame. In recent years, the desire to miniaturize, and provide higher density, semiconductor devices has caused the proliferation of, among other semiconductor devices, those known as SON (small outline non-leaded package) and QFN (quad flat non-leaded package) semiconductor devices.
Reference is made to
FIGS. 21-23
herein wherein this type of semiconductor device is shown at
10
. The semiconductor device
10
has leads
12
which do not project at a peripheral edge
14
of the semiconductor device
10
beyond a resin layer
16
. The leads
12
are exposed in this design at a back side
18
of the semiconductor device
10
.
It is known to manufacture semiconductor devices with substrates made from PCB, tape, and the like, practicing a manufacturing method known as a MAP process (mold array process). With this process, a sheet
20
is conventionally formed into a lead frame
22
with a base rail
24
connected to and surrounding a matrix of unit lead frames
26
, identified as A-I. Drive openings
27
facilitate manipulation of the base rail
24
. As described in greater detail below, the components of the semiconductor device
10
are built up upon the lead frame
22
, which is ultimately cut to separate the individual semiconductor devices
10
(in this case nine (9) in number) from each other and the base rail
24
. This process has been practiced to make the aforementioned SON and QFN semiconductor devices, as well as other types of semiconductor devices.
More particularly, in carrying out the MAP process to produce the semiconductor devices
10
, the lead frame
22
is formed as shown in FIG.
21
. Each unit lead frame
26
has a similar construction and, as shown for exemplary lead frame
26
at A, consists of a rectangular support
28
with four leads
12
at each of four outer edge portions
30
,
32
,
34
,
36
cooperatively defining the peripheral outer edge
38
of the support
28
. A semiconductor chip
40
is bonded to the support
28
using an adhesive or an adhesive tape
42
. Electrodes
44
on the semiconductor chip
40
are electrically connected to the leads
12
through conductive wires
46
.
The supports
28
, leads
12
, and base rail
24
are maintained in a desired relative position by a tie bar network
48
. The tie bar network
48
consists of a plurality of elongate tie bars, including support tie bars
50
, projecting in a diagonal direction each from a corner of the support, and peripheral tie bars
52
(numbered for the unit lead frame
26
at E), which extend around the perimeter of the individual unit lead frames
26
and interconnect with each other, the leads
12
, the support tie bars
50
, and the base rail
24
.
Once the semiconductor chips
40
are applied and electrically connected to the leads
12
, the resin layer
16
is applied in sealing fashion. The resin layer
16
is applied so as to simultaneously seal all of the unit lead frames
26
(A-I) continuously over the matrix of unit lead frames
26
within the square line
54
.
The individual semiconductor device
10
are separated and completed by strategically cutting a lead frame assembly, consisting of the lead frame
22
with the semiconductor chips
40
, conductive wires
46
, and resin layer
16
thereon, along lines indicated by the arrows A, and lines orthogonal thereto, as indicated by the arrows B. This effects separation of the semiconductor devices
10
from each other and the base rail
24
. This cutting may be effected using a saw with a width at least as large as the width W of the peripheral tie bars
52
.
The MAP process is desirable from the standpoint that the resin application can be carried out simultaneously for all of the semiconductor devices
10
. A single die can be used to facilitate the resin application. This process lends itself to being carried out efficiently and economically.
However, the MAP process described above, using the conventional structure shown in
FIGS. 21-23
, has a number of inherent problems. One problem results from the difference in the hardness of the material defining the lead frame
22
and the resin layer
16
. As the cutting blade cuts through the lead frame assembly, the resistance to cutting is different by reason of the different hardness of the two materials. As a result of this, there may be different deformation resulting from the cutting operation at different locations around the periphery of the semiconductor device
10
. This condition may cause a separation between the resin layer
16
and parts of the lead frame
22
at their interface. As just one example, this separation phenomenon is shown at
56
in
FIG. 23
where the resin layer
16
and lead frame
22
are bonded prior to performance of the cutting operation. Generally, this condition occurs in a downstream direction on a part of the lead frame
22
with respect to the cutting direction, as indicated by the arrows C in FIG.
23
.
An additional problem is that the cutting may form burrs
58
at the corners
59
to which the support tie bars
50
project. These burrs
58
likewise tend to form on the four tie bars
50
in a downstream region with respect to the cutting direction, as indicated by the arrow C. These burrs
58
not only affect the appearance and dimensions of the semiconductor devices
10
, but may also compromise the quality of an electrical connection to the semiconductor device
10
. To alleviate this problem, a separate deburring step may be required. This potentially complicates the manufacturing process and increases attendant costs.
SUMMARY OF THE INVENTION
In one form, the invention is directed to a lead frame for a semiconductor device. The semiconductor device has a sheet with oppositely facing sides and a thickness between the oppositely facing sides. The sheet has first and second unit lead frames. Each unit lead frame has a support for a semiconductor chip and at least one lead space from the support. The sheet has a tie bar network which connects a) the support to the at least one lead on each of the first and second lead frames and b) the first and second lead frames, each to the other. The sheet has a dividing line along which the sheet can be cut to separate the first and second lead frames from each other. The tie bar network consists of at least one tie bar extending along a substantial length of the dividing line. The support has a first thickness between the oppositely facing sides of the sheet. The at least one tie bar has a second thickness between the oppositely facing sides of the sheet over a substantial length of the dividing line that is less than the first thickness.
In one form, the base on the first unit lead frame has a polygonal shape with an outer edge defined by a plurality of straight edge portions. The dividing line is substantially straight and has a length and is spaced from, and extends substantially parallel to, one of the straight edge portions. The at least one tie bar has a thickness between the oppositely facing sides of the sheet that is less than the first thickness over substantially the entire length of the dividing line.
In one form, the first unit lead frame has a corner and the tie bar network consists of a support tie bar assembly including at least one support tie bar that extends from the support on the first unit lead frame towards the corner.
The second difference in the lead frame
142
is at the leads
66
′. Each lead
66
′ is formed with an undercut
160
along a substantial length thereof, which undercut resides fully within, and is spaced from, side edges bounding the width of the lead
66
′.
In one form, the support tie bar assemb
Dohki Yuichi
Etoh Hitoshi
Hanada Hideshi
Ishibashi Takahiro
Sugimoto Jun
Mitsui High-tec Inc.
Thai Luan
Wood Phillips Katz Clark & Mortimer
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