Lead frame design for chip scale package

Details Lead frame design for chip scale package Lead frame design for chip scale package

2000-06-09

2004-01-27

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000

Reexamination Certificate

active

06683368

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuit packages. More specifically, the invention relates to lead frames for the production of chip scale integrated circuit packages.
BACKGROUND OF THE INVENTION
An integrated circuit (IC) package encapsulates an IC chip (die) in a protective casing and may also provide power and signal distribution between the IC chip and an external printed circuit board (PCB). An IC package may use a metal lead frame to provide electrical paths for that distribution.
To facilitate discussion,
FIG. 1
is a top view of a lead frame panel
100
made up for a plurality of lead frames that may be used in the prior art. The lead frame may comprise leads
108
, die attach pads
112
, ties
116
for supporting the die attach pads
112
, and a skirt
120
for supporting the plurality of leads
108
and ties
116
. The lead frame panel
100
may be etched or stamped from a thin sheet of metal. IC chips
124
may be mounted to the die attach pads
112
by an adhesive epoxy. Wire bonds
128
, typically of fine gold wire, may then be added to electrically connect the IC chips
124
to the leads
108
. Each IC chip
124
may then be encapsulated with part of the leads
108
and the die attach pad
112
in a protective casing, which may be produced by installing a preformed plastic or ceramic housing around each IC chip or by dispensing and molding a layer of encapsulation material over all IC chips
124
.
FIG. 2
is a cross-sectional view of part of the lead frame panel
100
and IC chips
124
. In a process described in U.S. patent application Ser. No. 09/054,422, entitled “Lead Frame Chip Scale Package”, by Shahram Mostafazadeh et al., filed Apr. 2, 1998, a tape
136
is placed across the bottom of the lead frame panel
100
and a dam
132
is placed around the lead frame panel
100
. An encapsulation material
140
is poured to fill the dam
132
, encapsulating the IC chips
124
, the wire bonds
128
, and part of the lead frame panel
100
. The tape
136
prevents the encapsulation material
140
from passing through the lead frame panel
100
. Once the encapsulation material
140
is hardened, the dam
132
and tape
136
may be removed. The encapsulation material
140
may be cut to singulate the IC chips
124
and leads
108
.
It is desirable to provide an IC package process, which does not require the steps of adding tape to the lead frame and then removing the tape from the lead frame. It is also desirable to provide a process and lead frame that may accommodate various chip sizes and provides lead fingers.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a variety of techniques is provided for packaging of integrated circuits. Generally, a conductive substrate formed from a conductive material is patterned to define a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are physically mounted on a first portion of the plurality of posts, wherein each die is physically mounted on at least four posts. The dice are electrically connected to a second portion of the plurality of posts. A cap is molded over the plurality of dice and the patterned conductive substrate. The connecting sheet is then removed. Finally, integrated circuit packages are singulated.
Another aspect of the invention provides another method for packaging integrated circuits. Generally, a conductive substrate formed from a conductive material is patterned to define a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are physically mounted on a first portion of the plurality of posts. The dice are electrically connected to a second portion of the plurality of posts. A cap is molded over the plurality of dice and the patterned conductive substrate. The posts are separated to form lead fingers from the separated plurality of posts.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.


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U.S. patent application No. 09/698,784, entitled “Flip Chip Scale Package”, filed Oct. 26, 2000, inventor(s): Shahram Mostafazadeh.
U.S. patent application No. 09/698,736, entitled “Chip Scale Pin Array”, filed Oct. 26, 2000, inventor(s): Shahram Mostafazadeh.
U.S. patent application No. 09/054,422, entitled “Lead Frame Chip Scale Package”, by Shahram Mostafazadeh et al., filed Apr. 2, 1998.

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