Reexamination Certificate
1999-12-15
2002-08-06
Clark, Sheila V. (Department: 2815)
C257S666000, C257S787000, C438S123000, C438S124000
Reexamination Certificate
active
06427976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a lead-frame-based chip-scale package (CSP) and a method of manufacturing the same.
2. Description of Related Art
A chip-scale package (CSP), as the name implies, is an IC package whose overall size is nearly the same as the semiconductor chip packed therein. A CSP structure that is based on a lead frame for the attachment of the chip is customarily referred to as a lead-frame-based chip-scale package (hereinafter abbreviated as L/F-based CSP structure).
Conventionally, many various types of L/F-based CSP structures have been proposed and introduced to the market. For example, Fujitsu introduces a SON (Small Outline Non-Leaded) type of CSP structure; LG Semicon introduces a BLP (Bottom Leaded Plastic) type of CSP structure; Matsushita introduces a QFN (Quad Flat Non-Leaded) type of CSP structure; and Toshiba introduces a QON (Quad Outline Non-Leaded) type of CSP structure, to name just a few. All these types of CSP structures utilize a lead frame for chip attachment, and the inner leads of the lead frame have one side exposed to the bottom outside of the package body for electrically coupling to the surface of an external circuit board through SMT (Surface-Mount Technology).
One drawback to the forgoing types of L/F-based CSP structures, however, is that during the lead-singulation process to punch away the outer-lead part of the lead frame, it would easily cause micro cracks in the epoxy molding compound (EMC). This drawback is illustratively depicted in
FIGS. 1A-1C
, which respectively show a BLP type, a QFN type, and a QON type of CSP structure.
Referring to
FIG. 1A
, the BLP type of CSP structure is based on a lead frame
10
for the attachment of a semiconductor die
11
. The lead frame
10
is formed with an inner-lead part
10
a
and an outer-lead part
10
b.
After an EMC
12
is formed to encapsulate the semiconductor die
11
and the inner-lead part
10
a
of the lead frame
10
, a lead-singulation process is performed to punch away the exposed outer-lead part
10
b
of the lead frame
10
. The lead-singulation process, however, would cause micro cracks, as the part designated by the reference numeral
13
, in the EMC
12
right above the encapsulated inner-lead part
10
a.
Referring to
FIG. 1B
, the QFN type of CSP structure is based on a lead frame
20
for the attachment of a semiconductor die
21
. The lead frame
20
is formed with an inner lead part
20
a
and an outer-lead part
20
b.
After an EMC
22
is formed to encapsulate the semiconductor die
21
and the inner-lead part
20
a
of the lead frame
20
, a lead-singulation process is performed to punch away the exposed outer-lead part
20
b
of the lead frame
20
. The lead-singulation process, however, would also cause micro cracks, as the part designated by the reference numeral
23
, in the EMC
22
right above the encapsulated inner-lead part
20
a.
Referring to
FIG. 1C
, the QON type of CSP structure is based on a lead frame
30
for the attachment of a semiconductor die
31
. The lead frame
30
is formed with an inner-lead part
30
a
and an outer-lead part
30
b.
After an EMC
32
is formed to encapsulate the semiconductor die
31
and the inner-lead part
30
a
of the lead frame
30
, a lead-singulation process is performed to punch away the exposed outer-lead part
30
b
of the lead frame
30
. The lead-singulation process, however, would likewise cause micro cracks, as the part designated by the reference numeral
33
, in the EMC
32
right above the encapsulated inner-lead part
30
a.
The occurrence of the above-mentioned micro-cracks is due to the reason that the inner-lead part has only one side bonded to the EMC while the other side is exposed to the bottom outside of the EMC. The exposed side is hence lack of firm support against the punching force during the lead-singulation process.
One solution to the foregoing problem is disclosed in Toshiba's U.S. Pat. No. 5,703,407, which is illustrated in FIG.
1
D. As shown, this patented package structure is based on a lead frame
40
for the attachment of a semiconductor die
41
. The lead frame
40
is formed with an inner-lead part
40
a
and an outer-lead part
40
b.
Further, an EMC
42
is formed to encapsulate the semiconductor die
41
and the inner-lead part
40
a
of the lead frame
40
. After this, a lead-singulation process is performed to punch away the exposed outer-lead part
40
b
of the lead frame
40
. This patent is characterized in the step of performing a half-etching process on the inner-lead part
40
a
of the lead frame
40
, which can help strengthen the bonding between the EMC
42
and the stop side of the inner-lead part
40
a
of the lead frame
40
so that it would become more resistible against the punching force during the lead-singulation process. One drawback to this solution, however, is that the half-etching technology is quite costly to use, and thus it would considerably increase the overall manufacture cost of the IC package.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide an L/F-based CSP structure and a method of manufacturing the same, which can help prevent the lead-singulation process from causing micro cracks in the EMC.
It is another objective of this invention to provide an L/F-based CSP structure and a method of manufacturing the same, which can be implemented without having to use the high-cost half-etching technology.
In accordance with the foregoing and other objectives, the invention proposes a new CSP structure and a method of manufacturing this CSP structure. The proposed CSP structure comprises: a lead frame having a plurality of inner leads, with each inner lead being formed with a deformed portion; at least one semiconductor die mounted on the lead frame; a set of bonding wires for electrically coupling the semiconductor die to the inner leads; and an EMC for encapsulating the semiconductor die, the bonding wires, and the inner leads, wherein both sides of each inner lead can be wrapped by the EMC due to each inner lead being raised by the deformed portion to within the EMC. During the lead-singulation process, the outer-lead part of the lead frame is punched away.
By the invention, both sides of the inner-lead part can be wrapped by the EMC due to it being raised to a predetermined height from the bottom side of the entire package body by the deformed portion. As a result, during the lead-singulation process, the inner-lead part can be firmly supported in position, thereby reducing the occurrence of micro cracks in the EMC above the inner-lead part that would otherwise occur in the prior art.
REFERENCES:
patent: 5157480 (1992-10-01), McShane et al.
patent: 5428248 (1995-06-01), Cha
patent: 5834837 (1998-11-01), Song
patent: 5898216 (1999-04-01), Steffen
patent: 5977613 (1999-11-01), Takata et al.
patent: 5998877 (1999-12-01), Ohuchi
patent: 6329705 (2001-12-01), Ahmad
Huang Chien Ping
Ko Eric
Clark Sheila V.
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
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