Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2002-12-20
2004-10-26
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S666000
Reexamination Certificate
active
06809409
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices incorporating a lead frame defining a support for a semiconductor chip and a plurality of leads.
2. Background Art
There has been a trend in recent years to minimize the size of semiconductor devices. This makes possible the compact and lightweight construction of electronic appliances, and the like, incorporating the semiconductor devices. As examples of appliances, for which size and weight are key design considerations, are portable telephones, PDA devices, as well as myriad other portable electronic appliances used in many diverse environments and for different purposes. Various designs of semiconductor devices have evolved over the years to achieve the ends of miniaturization, thickness reduction and weight reduction. These devices are commonly referred to as TBGA that use a lead frame and TAB (tape automated bonding) tape, PBGA, and CSP (chip size package) that use flexible printed circuit boards. Options include wafer-scale CSP, which is the same size as the chip, and CSP, which is somewhat larger than the chip.
Of these devices, particular interest has been paid to semiconductor devices of the type wherein leads are exposed at a flat face within the confines of a resin sealed package, rather than on the edges thereof. Exemplary packages are those referred to as SON (small outline non-leaded package) and QFN (quad flat non-leaded package).
An exemplary, conventional, QFN-type semiconductor device is shown at
10
in
FIGS. 15-17
. The semiconductor device
10
has a unit lead frame
12
which defines a support
14
and a plurality of leads
16
spaced around the support
14
. The lead frame
12
has a first planar surface
18
, facing in a first direction, and a second planar surface
20
, facing oppositely to the first surface
18
. The first and second surfaces
18
,
20
reside respectively in spaced, parallel, reference planes P
1
, P
2
. The support
14
has a surface portion
22
upon which a semiconductor device
24
is mounted. The semiconductor device
24
is electrically connected to the leads
16
through conductive wires
26
. The support
14
, leads
16
, semiconductor device
24
, and conductive wires
26
are embedded in a sealing resin
28
. A surface portion
30
on the support
14
, facing oppositely to the surface portion
22
, is exposed at the second reference plane P
2
.
With this construction, the leads
16
do not protrude from straight edges
32
,
34
,
36
,
38
which cooperatively bound the polygonal shape of the semiconductor device
10
. The leads
16
have surface portions
40
which are coplanar with the surface portion
30
on the support
14
and are coplanar with, and exposed at, the reference plane P
2
. This accounts for an overall compact arrangement with flat mounting locations.
FIG. 23
shows the semiconductor device
10
mounted upon a printed circuit board
42
. The printed circuit board
42
has a circuit pattern
44
thereon coated with a resist layer
46
. The resist layer
46
provides an insulating barrier in those regions which do not need to be exposed for electrical connection, as to the leads
16
. First portions
48
,
50
of the circuit pattern
44
exposed through the resist layer
46
are electrically connected to the leads
16
through solder
52
.
The semiconductor device
10
may be made by a MAP (mold array package) process. With this process, the lead frame
12
has a configuration as shown in FIG.
24
. The lead frame
12
consists of a sheet
54
of conductive material that is processed to produce a matrix pattern of unit lead frames A, B, C, D, E, F, G, H, I, J, K, L, M, N, O. Each of the unit lead frames (A-O) has the same construction as the exemplary lead frame at C, shown in detail in
FIGS. 15-17
and
23
. Each unit lead frame A-O consists of a support
14
with surrounding leads
16
interconnected and maintained in an operative relationship by a tie bar network at
56
. Side rails
58
,
60
are used to controllably reposition the sheet
54
. The pattern of the supports
14
, leads
16
, and tie bar network
56
can be made through an etching process using a mask with a resist pattern with these elements thereon, or by other processes known to those skilled in the art.
The steps involved in manufacturing the semiconductor devices
10
from the lead frame
12
, using a conventional process, will now be described with respect to
FIGS. 18-22
.
A film layer
64
, as show in
FIG. 19
, is applied to the second surface
20
of the lead frame in
FIG. 18
to control the flow of the sealing resin
28
at the second surface
20
. A shown in
FIG. 20
, the semiconductor device
24
is applied to the surface portion
22
of the support
14
and is electrically connected to the leads
16
through the wires
26
.
As shown in
FIG. 21
, the sealing resin
28
is then applied using cooperating mold parts
66
,
68
so that the semiconductor chip
24
and wires
26
are fully encased within the sealing resin
28
, resulting in the formation of a preassembly at
70
.
Once the sealing resin
28
is cured, the preassembly
70
is strategically cut to define individual semiconductor devices
10
. To complete the exemplary semiconductor device
10
, made from the lead frame C, the preassembly
70
is cut along lines L
1
, L
2
, shown in
FIGS. 22 and 24
, and along orthogonal lines L
3
, L
4
, shown in FIG.
24
. The cutting can be carried out in a conventional process, as by using a cutting blade.
The conventional semiconductor device
10
, of the type shown in
FIGS. 15-24
, may have a number of problems that are inherent to the design. First of all, there is a tendency of the sealing resin
28
to peel at the interface between the peripheral edge
72
of the support
14
and the sealing resin
28
. This interface may also be the cause of warping of the semiconductor device package.
Another problem with the conventional design described herein is that the relatively thin resist layer
46
, as shown in
FIG. 23
, is the only insulating structure between the support
14
and the circuit pattern
44
on the printed circuit board
42
. Thus, there is a risk that the support
14
may detrimentally make electrical contact with the circuit pattern
44
.
Another drawback with the conventional design is the requirement for the film layer
64
, which is applied after the formation of the lead frame
12
. The film layer
64
is applied before the attachment of the semiconductor chips
24
, the conductive wires
26
, and the molding of the sealing resin
28
. During these processes, the surface portion
30
of the support
14
is supported upon, and acted against by, a heater plate. This may make more difficult the removal of the film layer
64
from the support
14
required to complete the semiconductor device
10
.
SUMMARY OF THE INVENTION
In one form, the invention is directed to a lead frame having a body with oppositely facing, substantially planar, first and second surfaces respectively facing in first and second directions and residing in first and second substantially parallel reference planes. The body defines a support for a semiconductor chip and a plurality of leads. The support has a third surface facing in the first direction, to which a semiconductor chip can be mounted, and a fourth surface facing in the second direction. At least a part of the fourth surface is spaced from the second reference plane towards the first reference plane.
In one form, at least a part of the fourth surface is planar and resides in a fourth reference plane that is substantially parallel to the first and second reference planes.
A first discrete projection may project from the fourth surface in the second direction.
In one form, the first discrete projection is formed as one piece with at least a part of the support. Alternatively, the first discrete projection may be formed separately from the support and secured to the support.
In one form, the first projection may be secured to the support through an insulating member.
In one form,
Fukui Atsushi
Tsujimoto Keiichi
Clark S. V.
Mitsui High-tec Inc.
Wood Phillips Katz Clark & Mortimer
LandOfFree
Lead frame and semiconductor device made using the lead frame does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lead frame and semiconductor device made using the lead frame, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lead frame and semiconductor device made using the lead frame will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3272367