Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-29
2002-07-23
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C029S830000, C029S831000, C029S832000
Reexamination Certificate
active
06423622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a lead-bond type chip package, and more specifically to a multilayer substrate for use in forming the lead-bond type chip package. This invention also pertains to a method for making the multilayer substrate.
2. Description of the Related Art
FIG. 1
depicts a conventional lead-bond type chip package
100
comprising a semiconductor chip
130
disposed on a substrate
120
through an elastomer pad
110
. The semiconductor chip
130
has a plurality of bonding pads
132
disposed thereon. The substrate
120
includes a plurality of solder pads
122
and leads
124
provided on the upper surface thereof. The solder pads
122
are electrically connected to corresponding leads
124
through conductive traces on the substrate
120
. The substrate
120
has a plurality of through-holes corresponding to the solder pads
122
such that each of the solder pads
122
has at least a portion exposed from its corresponding through-hole for mounting a solder ball
126
. The leads
124
are bonded to corresponding bonding pads
132
thereby electrically connecting the semiconductor chip
130
to the substrate
120
. A package body
140
is formed around the semiconductor chip
130
and filled the slot
120
a
of the substrate
120
. The package body
140
is formed from insulating material such as epoxy resin.
The substrate
120
is typically made from flexible polyimide film; hence, it is prone to be deformed by external forces (e.g. stress due to CTE (coefficient of thermal expansion) mismatch) thereby resulting in problems of die cracking or delamination. Further, since the substrate
120
only has a layer of conductor circuit (i.e. the solder pads
122
, the leads
124
, and the conductive traces), it is difficult to provide enough power and ground planes. Therefore, the conventional lead-bond type chip package
100
does not provide a good signal plane for current surges into or out of the semiconductor chip
130
. The relatively poor electrical performance associated with the package
100
is especially apparent when the semiconductor chip
130
includes high density, high frequency digital circuitry.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial number of I/O connections. Therefore, it will possibly happen that some of the I/O connections of a chip can not be lead-bonded for electrical connection due to the insufficiency of wiring density in the substrate with a single layer of conductor circuit. If this were the case, multiple layer structure will be required for the chip with high I/O connections.
The present invention therefore seeks to provide a lead-bond type chip package which overcomes, or at least reduces the above-mentioned problems of the prior art.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a lead-bond type chip package comprising a multilayer substrate capable of providing enough power and ground planes thereby enhancing the electrical performance of the package.
It is another object of the present invention to provide a lead-bond type chip package comprising a multilayer substrate with enhanced mechanical strength thereby reducing problems of die cracking or delamination.
Accordingly, in a first aspect, the present invention provides a lead-bond type chip package including a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having a dielectric layer formed thereon, a plurality of leads on the dielectric layer on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection disposed on the dielectric layer on the lower surface of the interlayer circuit board. The solder pads are electrically connected to corresponding leads. The interlayer circuit board has conductor circuits formed therein. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate.
Preferably, the interlayer circuit board is formed from a core layer made of fiberglass reinforced BT (bismaleimide-triazine) resin or FR-4 fiberglass reinforced epoxy resin thereby increasing the mechanical strength of the multilayer substrate. The interlayer circuit board comprises at least a ground plane (or a power plane) formed therein for enhancing the electrical performance of the lead-bond type chip package. Moreover, the dielectric layer on the interlayer circuit board is preferably formed from prepreg which comprises a semi-cured thermosetting resin as well as glass fibers dispersed therein whereby the mechanical strength of the multilayer substrate is further increased.
According to a second aspect, this invention further provides a method of producing a multilayer substrate for use in forming a lead-bond type chip package comprising the steps of (a) providing an interlayer circuit board in which conductor circuits have been formed, the interlayer circuit board having a dielectric layer formed thereon and a slot defined therein; (b) providing a first copper foil with one surface coated by a etch-resistant layer; (c) laminating on one surface of the interlayer circuit board the first copper foil, and the other surface of the interlayer circuit board a second copper foil in a manner that the etch-resistant coated surface of the first copper foil is in contact with the dielectric layer on the interlayer circuit board; (d) selectively etching the copper foils laminated on the interlayer circuit board so as to form fine holes at predetermined positions thereof; (e) applying laser beams to the prepreg exposed from the fine holes of the copper foils so as to form via holes and expose parts of the conductor circuits of the interlayer circuit board; (f) forming through-holes; (g) plating a metal layer to electrically connect the conductor circuits of the interlayer circuit board and the copper foils; (h) selectively etching the first copper foil and the plated metal layer thereon to form a plurality of leads adapted for electrically connecting to a semiconductor chip wherein each of the leads has at least a portion across the slot of the interlayer circuit board, and selectively etching the second copper foil and the plated metal layer thereon to form a predetermined configuration and expose the slot of the interlayer circuit board; (i) stripping the etch-resistant coated on the first copper foil exposed within the slot of the interlayer circuit board; (j) forming a solder mask on the patterned surfaces of the multilayer substrate in a manner that areas on the leads for electrically connecting to a semiconductor chip and solder pads for making external electrical connection are exposed from the solder mask; and (k) forming a metal coating on the solder pads and the exposed portions of the leads. In a preferred embodiment, the step of (a), (b), and (c) described above can be replaced by (a′) providing an interlayer circuit board in which conductor circuits have been formed, the interlayer circuit board having a slot defined therein; (b′) providing a first copper foil with one surface coated by an etch-resistant layer; and (c′) laminating on one surface of the interlayer circuit board the first copper foil, and the other surface of the interlayer circuit board a second copper foil via a plurality of prepregs wherein the etch-resistant coated surface of the first copper foil is in contact with one of the prepreg, and each pr
Chen Kun-Ching
Yeh Yung I
Advanced Semiconductor Engineering Inc.
Geyer Scott B.
Sherry Michael J.
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