LDPC decoding methods and apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S776000

Reexamination Certificate

active

07395490

ABSTRACT:
A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

REFERENCES:
patent: 3542756 (1970-11-01), Gallager
patent: 3665396 (1972-05-01), Forney, Jr.
patent: 4295218 (1981-10-01), Tanner
patent: 5157671 (1992-10-01), Karplus
patent: 5271042 (1993-12-01), Borth et al.
patent: 5293489 (1994-03-01), Furui et al.
patent: 5313609 (1994-05-01), Baylor et al.
patent: 5396518 (1995-03-01), How
patent: 5457704 (1995-10-01), Hoeher et al.
patent: 5526501 (1996-06-01), Shams
patent: 5615298 (1997-03-01), Chen
patent: 5671221 (1997-09-01), Yang
patent: 5860085 (1999-01-01), Stormon et al.
patent: 5864703 (1999-01-01), Van Hook et al.
patent: 5867538 (1999-02-01), Liu
patent: 5892962 (1999-04-01), Cloutier
patent: 5933650 (1999-08-01), van Hook et al.
patent: 5968198 (1999-10-01), Hassan
patent: 6002881 (1999-12-01), York et al.
patent: 6073250 (2000-06-01), Luby et al.
patent: 6195777 (2001-02-01), Luby et al.
patent: 6247158 (2001-06-01), Smallcomb
patent: 6266758 (2001-07-01), van Hook et al.
patent: 6298438 (2001-10-01), Thayer et al.
patent: 6339834 (2002-01-01), Crozier et al.
patent: 6397240 (2002-05-01), Fernando et al.
patent: 6438180 (2002-08-01), Kavcic et al.
patent: 6473010 (2002-10-01), Viyaev et al.
patent: 6484284 (2002-11-01), Smallcomb
patent: 6526538 (2003-02-01), Hewitt
patent: 6633856 (2003-10-01), Richardson et al.
patent: 6718504 (2004-04-01), Coombs et al.
patent: 6724327 (2004-04-01), Pope et al.
patent: 6731700 (2004-05-01), Yakhnich et al.
patent: 6754804 (2004-06-01), Hudepohl et al.
patent: 6842873 (2005-01-01), McLaughlin et al.
patent: 6940431 (2005-09-01), Hayami
patent: 7222284 (2007-05-01), Stolpman
patent: 7251769 (2007-07-01), Ashikhmin et al.
patent: 2002/0042899 (2002-04-01), Tzannes et al.
patent: 2004/0034828 (2004-02-01), Hocevar
patent: 2004/0098659 (2004-05-01), Bjerke et al.
patent: 2005/0050435 (2005-03-01), Kyung et al.
patent: 2005/0154958 (2005-07-01), Xia et al.
patent: 2005/0229088 (2005-10-01), Tzannes et al.
patent: 2005/0246617 (2005-11-01), Kyung et al.
patent: 2006/0031734 (2006-02-01), Stolpman
Singla et. al., Iterative Decoding and Equalization for 2-D Recording Channels, Sep. 2002, IEEE, vol. 38. No. 5, pp. 2328-2330.
T. Richardson and R. Urbanke, “The Capacity of Low-Density Parity-Check Codes under Message-Passing Decoding”, pp. 1-44 (Mar. 2001).
Saied Hemati, Amir H. Banihashemi, VLSI circuits: Iterative decoding in analog CMOS, Proceedings of the 13thACM Great Lakes Symposium on VLSI Apr. 2003, pp. 15-20.
Mohammad M. Mansour, Naresh R. Shanbhag, Session 11: Low-power VLSI decoder architectures for LDPC codes, Proceedings of the 2002 international symposium on Low power electronics and design Aug. 2002, pp. 284-289.
Richardson et al. “The capacity of low-density parity-check codes under message-passing Decoding”, IEEE Transactions on Information Theory; pp. 599-618, Feb. 2001, (same inventor) whole document.
Paranchych et al. “Performance of a digital symbol synchronizer in cochannel interference and noise”, IEEE Transactions on Communications, pp. 1945-1954; Nov. 2000, whole document.
Sorokine, V. et al. “Innovative coding scheme for spread-spectrum communications”, The Ninth IEEE International Symposium on Indoor and Mobile Radio Communications, pp. 1491-1495, vol. 3; Sep. 1998, whole document.
NN77112415. “Digital Encoding of Wide Range Dynamic Analog Signals”, IBM Tech. Disclosure Bulletin, Nov. 1, 1997, vol. No. 20; Issue No. 6; pp. 2415-2417, whole document.
NN9210335. “Hierarchical Coded Modulation of Data with Fast Decaying Probability Distributions”, IBM Tech. Disclosure Bulletin, Oct. 1992, vol. No. 35; Issue No. 5; pp. 335-336, whole document.
T. Richardson and R. Urbanke, “An Introduction to the Analysis of Iterative Coding Systems”, pp. 1-36.
T. Richardson, A. Shokrollahi, R. Urbanke, “Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes”, pp. 1-43 (Mar. 2001).
T. Moors and M. Veeraraghavan, “Preliminary specification and explanation of Zing: An end-to-end protocol for transporting bulk data over optical circuits”, pp. 1-55 (May 2001).
R. Blahut, “Theory and Practice of Error Control Codes”, Library of Congress Cataloging in Publication Data, pp. 47-49, (May 1984).
W. W. Peterson and E.J. Weldon, Jr., “Error-Correcting Codes”, Second Edition, The Massachusetts Institute of Technology, pp. 212-213,261-263, 263, (1986).
Richardson et al. “The capacity of low-density parity-check codes under message-passing Decoding”, IEEE Transactions on Information Theory; pp. 599-618, Feb. 2001, (same inventor) whole document.
Paranchych et al. “Performance of a digital symbol synchronizer in cochannel interference and noise”, IEEE Transactions on Communications, pp. 1945-1954; Nov. 2000, whole document.
Sorokine, V. et al. “Innovative coding scheme for spread-spectrum communications”, The Ninth IEEE International Symposium on Indoor and Mobile Radio Communications, pp. 1491-1495, vol. 3; Sep. 1998, whole document.
NN77112415. “Digital Encoding of Wide Range Dynamic Analog Signals”, IBM Tech. Disclosure Bulletin, Nov. 1, 1997, vol. No. 20; Issue No. 6; pp. 2415-2417, whole document.
NN9210335. “Hierarchical Coded Modulation of Data with Fast Decaying Probability Distributions”, IBM Tech. Disclosure Bulletin, Oct. 1992, vol. No. 35; Issue No. 5; pp. 335-336, whole document.
T. Richardson and R. Urbanke, “An Introduction to the Analysis of Iterative Coding Systems”, pp. 1-36, 2001.
T. Richardson, A. Shokrollahi, R. Urbanke, “Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes”, pp. 1-43 (Mar. 2001).
T. Moors and M. Veeraraghavan, “Preliminary specification and explanation of Zing: An end-to-end protocol for transporting bulk data over optical circuits”, pp. 1-55 (May 2001).
R. Blahut, “Theory and Practice of Error Control Codes”, Library of Congress Cataloging in Publication Data, pp. 47-49, (May 1984).
W. W. Peterson and E.J. Weldon, Jr., “Error-Correcting Codes”, Second Edition, The Massachusetts Institute of Technology, pp. 212-213,261-263, 263, (1986).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

LDPC decoding methods and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with LDPC decoding methods and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LDPC decoding methods and apparatus will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3970239

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.