LDPC code and encoder/decoder regarding same

Details LDPC code and encoder/decoder regarding same LDPC code and encoder/decoder regarding same

2006-10-10

2006-10-10

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

Reexamination Certificate

active

07120856

ABSTRACT:
A joint code-encoder-decoder design approach and circuit architecture design for (3,k)-regular LDPC coding system implementation. The joint design process relies on a high girth (2,k)-regular LDPC code construction. The decoder realizes partly parallel decoding. The encoding scheme only contains multiplications between sparse matrices and vector and multiplication between a very small dense matrix and vector.

REFERENCES:
Richardson et al., THe capacity of low density parity check codes under message passing decoding, Feb. 2001, IEEE Trans. on Info. Theory, vol. 47, No. 2, pp. 599-618.
Kurkoski et al. Joint message passing decoding of LDPC codes and parital response channels, Jun. 2002, IEEE trans. on Info. Theory, vol. 48, No. 6, pp. 1410-1422.
Mehta et al. An FPGA implementation of the graph encoder-decoder for regular LDPC codes, Aug. 2002, www.google.com, pp. 1-18. printed Jun. 2, 2006.

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