Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-02
2004-12-21
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S492000, C257S493000, C257S409000
Reexamination Certificate
active
06833586
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors and, in particular, to an N-type LDMOS transistor using a thick oxide layer as the gate dielectric.
DESCRIPTION OF THE RELATED ART
Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are commonly used in high-voltage applications (20 to 500 volts) because of their high breakdown voltage characteristics and compatibility with CMOS technology for low voltage devices.
FIG. 1
is a cross-sectional view of a conventional N-type LDMOS transistor. It is well known that by increasing the length of the drift region, denoted by the distance “d”, the breakdown voltage of the LDMOS transistor can be accordingly increased.
Conventional LDMOS transistors are uni-directional devices. That is, the drain and source terminals of the conventional LDMOS transistors are not interchangeable. Referring to
FIG. 1
, the gate dielectric of the LDMOS transistor includes a gate oxide layer on top of the channel region (that is, the p-well body) of the LDMOS transistor. The drift region is formed between the channel region and the drain terminal. As a result of the non-symmetrical structure, only the drain terminal of the conventional LDMOS transistor is designed to handle high voltage. The source and gate terminals are not designed to withstand high voltages.
Thus, in the conventional LDMOS transistors, the drain to gate voltage, drain to source voltage and drain to substrate voltage can be high voltages while the gate to substrate voltage, the gate to source voltage and source to substrate voltage are limited to low voltages. Specifically, the gate to substrate voltage is limited by the breakdown voltage of the gate oxide layer. The gate to source voltage is limited to “gated” or “gate assisted” breakdown voltage of the LDMOS transistor. The source to substrate voltage is limited by the breakdown voltage of the junction associated with the source terminal. Hence, the gate and source voltage swing of the conventional LDMOS transistor is limited and the gate and source terminals of such conventional LDMOS transistors cannot be driven by a high voltage device.
Therefore, it is desirable to optimize the breakdown voltage characteristics of an LDMOS transistor such that the gate, source and drain terminals of the LDMOS transistor can all withstand high voltages.
SUMMARY OF THE INVENTION
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes drift regions from the body to both the drain and the source terminals of the transistor such that both the drain and the source terminals are disposed to withstand high voltages.
In one embodiment, a transistor includes a semiconductor layer of a first conductivity type, a first well of a second conductivity type formed in the semiconductor layer where the first well forms a body region of the transistor, and a first dielectric layer formed on the top surface of the semiconductor layer where the first dielectric layer forms a gate dielectric layer of the transistor. A portion of the first dielectric layer is formed over the first well and remaining portions of the first dielectric layer is formed over the semiconductor layer on either side of the first well. The transistor further includes a second dielectric layer formed on the top surface of the semiconductor layer and encircling the first dielectric layer, a conductive gate formed over the first dielectric layer and located above the first well, a first region of the first conductivity type formed in the semiconductor layer abutting a first edge of the second dielectric layer, and a second region of the first conductivity type formed in the semiconductor layer abutting a second edge of the second dielectric layer opposite the first edge.
As thus formed, the transistor includes a first drift region between the body region and the first region and a second drift region between the body region and the second region. The first drift region is formed in the semiconductor layer between a first edge of the first well to the first edge of the second dielectric layer. The second drift region between the body region and the second region is formed in the semiconductor layer between a second edge of the first well, opposite the first edge of the first well, to the second edge of the second dielectric layer.
According to one aspect of the present invention, either the first region or the second region can be used to form a source region of the transistor. The other one of the first and second regions forms a drain region of the transistor. Accordingly, the drain and source region of the transistor is interchangeable.
According to another aspect of the present invention, the first dielectric layer and the second dielectric layer are formed as a contiguous field oxide layer. The field oxide layer can have a thickness of about 6500 Å.
According to another aspect of the present invention, the second dielectric layer is a field oxide layer and the first dielectric layer is an oxide layer having a thickness less than the field oxide layer. In one embodiment, the first dielectric layer is a thin gate oxide layer.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
REFERENCES:
patent: 4300150 (1981-11-01), Colak
patent: 5047820 (1991-09-01), Garnett
patent: 5406110 (1995-04-01), Kwon et al.
patent: 5517046 (1996-05-01), Hsing et al.
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patent: 6096589 (2000-08-01), Lee et al.
patent: 6211552 (2001-04-01), Efland et al.
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 6525376 (2003-02-01), Harada et al.
Cook Carmen C.
Loke Steven
Micrel Inc.
Patent Law Group LLP
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