LDMOS transistor with enhanced termination region for high...

Details LDMOS transistor with enhanced termination region for high... LDMOS transistor with enhanced termination region for high...

2005-07-19

2005-07-19

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S287000, C257S336000, C257S341000, C257S342000, C257S343000, C257S339000, C257S409000, C257S496000

Reexamination Certificate

active

06919598

ABSTRACT:
A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

REFERENCES:
patent: 5258636 (1993-11-01), Rumennik et al.
patent: 5633521 (1997-05-01), Koishikawa

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