Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With housing mount
Reexamination Certificate
2000-07-21
2002-10-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With housing mount
C257S728000, C257S670000, C257S673000, C257S675000
Reexamination Certificate
active
06462413
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to powder metallurgy and the manufacture of micro-electronic packages and heat-dissipating elements thereof, and more particularly to heat-dissipating RF power transistor heatsinks and packaging.
BACKGROUND OF THE INVENTION
Radio frequency (“RF”) communications rely on high power transistors to boost the power of RF signals being sent to transmitting antennae. Recently the increasing demand for high bandwidth mobile phone service has caused a need for an assortment of high frequency (about 500 MHz to 2.5 GHz), relatively high power (about 30 to 250 watt) power transistors. Banks of such devices are used for example in mobile phone base stations.
A useful model has been the solid state double diffuse metal oxide silicon (“DMOS”) type transistor, which is a field effect transistor formed on a semiconductor chip or die having a source, a gate and a drain which are electrically connected to metalized pads on the die's surface which are wirebonded to a leadframe which electrically connects to other circuit devices. The die is mounted on a heatsink which is integral with the transistor package.
Prior DMOS designs such as Vertical DMOS suffered from requiring the die to be mounted upon an electrically isolating layer of relatively costly, thermally efficient ceramic material such as aluminum nitride, or more typically, beryllium oxide which is difficult to manufacture due to raw beryllium toxicity.
An effort to overcome this problem resulted in the development of a Lateral DMOS (“LDMOS”) transistor which does not require such electrical isolation along its mounting surface. Indeed, electrical contact to the transistor source is now had through the mounting surface, thereby requiring that it be conductive.
Referring now to
FIG. 1
, there is shown a prior art heatsink assembly
1
carrying a single LDMOS die
2
. Other multi-chip LDMOS package designs are also available. The assembly comprises a heat-dissipating substrate commonly referred to as a “flange”
3
, a dielectric insulator commonly referred to as a sealring or spacer
4
bonded to the flange which electrically isolates the flange from a conductive lead frame formed by two separate plates
5
,
6
bonded atop the spacer. The thickness of the spacer is selected to carry the leadframe at the proper height in relation to the die, and can be selected to change the electrical characteristics of the package.
The source of the transistor is electrically connected to the bottom of the die
2
and when packaged is electrically accessible through the conductive gold plated heatsink flange
3
upon which it is mounted. The gate and drain are connected to pads
7
,
8
on an upper surface of the die and are connected through wirebonds
9
to the conductive lead frame which extends out to form the package gate and drain leads
5
,
6
. Once these interconnections have been formed, the die is encapsulated by a plastic or ceramic lid (Not Shown) bonded to the assembly.
The flange
3
is made of heat-dissipating or otherwise thermal conductivity enhanced material which typically has a coefficient of thermal expansion (“CTE”) compatible with material forming the transistor which is typically gallium arsenide (“GaAs”) or silicon. For example, the flange may be formed from a sintered mixture of copper and tungsten powders whose concentrations have been selected to achieve a compatible CTE as disclosed in Polese et al., U.S. Pat. No. 5,886,407 fully incorporated herein by this reference.
The spacer
4
is typically made from a ceramic such as alumina or other electrically insulating material capable of being bonded to the flange and having a CTE compatible with the CTE of the flange material.
The heatsink assembly including flange, spacer and leadframe is fabricated prior to die attach. The leadframe is bonded to the spacer, and the spacer is bonded to the flange. Typically, both bonds are formed using high temperature Cu—Ag braze alloys, commonly known as CuSil brazing. The die
2
is then attached to the flange
3
through the central aperture
10
of the spacer using gold-silicon eutectic brazing. This type of brazing involves heating the flange to about 400° C., then typically placing the die manually under the aid of a microscope to avoid damaging the leadframe or spacer. At this temperature the thin layer of gold plating on the upper surface of the flange combines with the lower surface of the silicon die to form gold-silicon eutectic.
This type of brazing is preferred due to its low cost, high thermal conductivity, the ruggedness of the bond generated, and its uniformity across a given production run. However, it requires that the prior leadframe/spacer/flange bonds be capable of withstanding temperatures of at least about 400° C. Therefore, unfortunately, other popular low temperature bonding techniques such as soldering and adhesive bonding have been ruled out.
These techniques include soldering, and the use of various conductive adhesives. The most common solder alloys available comprise two or more of the following elements: Au, Ag, Ge, In, Pb, Sb and Sn which are applied at temperatures ranging from about 150 to 400° C. Although these techniques may result in bonds which do not enjoy the same thermal performance as CuSil brazing, their availability would afford the manufacturer greater flexibility in device design and capability.
Another problem with the above approach is that die attach is typically handled manually. This is partially due to the fact that unlike earlier bipolar transistor packaging where the die was mounted upon a ceramic substrate having recognizable patterns, the metallic heatsink flange die attach area has not such targeting features. In addition, during the attachment process, the flange/spacer/leadframe subassembly is first heated on a hot plate to about 400° C. Then, under a microscope the die is placed with a slight side-to-side or circular motion and under slight pressing to encourage the formation of a uniform bonding layer of eutectic Au—Si. Although greater automation would be possible, the presence of the relatively sensitive leadframe/spacer which can be of a greater variety of shapes and sizes makes automation difficult especially for low volume production runs. Therefore, manual die attach is still used even though it involves costly human interaction and results in greater variation in device performance across a given production lot, reducing yield and increasing cost for devices of a given tolerance.
Another problem is that the high temperature necessary for the CuSil bonding of the spacer-to-flange can cause a slight warping of the spacer that can degrade the flange-to-spacer bond. The overall thickness of the spacer and leadframe is restricted to the upper surface of the die so as to accommodate wirebonding.
Another problem involves the preferred use of gold plating on the flange and lead frame to provide good electrical conductivity and good corrosion resistance to the connections in the packages such as the wire bonds. However, most amplifier manufacturers use tin-lead based solder for interconnecting the RF power transistor packages. Such solder can be metallurgically incompatible with gold. Therefore, connections to the gold plated leads has less than optimum reliability.
Finally, there is the intricate and hence expensive and time-consuming process of wire-bonding the die electrical contacts to the leadframe contacts. Clearly minimizing or eliminating such a process would be desirable.
In general, the above package fabrication techniques are holdovers from the earlier VDMOS and bipolar transistor packaging techniques. Due to the new LDMOS architecture, there is now an opportunity to further automate the LDMOS packaging process.
The instant invention results from an attempt to devise a simpler and more practical process to manufacture such heat-dissipating structures and packages for LDMOS transistors.
SUMMARY OF THE INVENTION
The principal and secondary objects of the invention are to provide a practical and automatable process to package LDM
Graham Dana R.
Polese Frank J.
Weinshanker Stuart
Buchaca John D.
Charmasson Henri J. A.
Ho Tu-Tu
Nelms David
Polese Company, Inc.
LandOfFree
LDMOS transistor heatsink package assembly and manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with LDMOS transistor heatsink package assembly and manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LDMOS transistor heatsink package assembly and manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2946723