Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-23
2003-07-15
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S339000, C257S340000
Reexamination Certificate
active
06593621
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors and, in particular, to an LDMOS transistor with improved ruggedness at curved areas.
2. Description of the Related Art
Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are commonly used in high-voltage applications because of their high breakdown voltage characteristics.
FIG. 1
is a cross-sectional view of a conventional LDMOS transistor. It is well known that by increasing the length of the drift region, denoted by the distance “d”, the breakdown voltage of the LDMOS transistor can be accordingly increased.
Device modelling typically involves only two-dimensional (2D) analysis of an LDMOS transistor (that is, the depth and the length of the transistor). Such 2D modelling neglects three-dimensional effects on the surface of the transistor. It is well known that the layout geometry of an LDMOS transistor can have an adverse impact on device characteristics, such as the breakdown voltage, of the transistor. Specifically, when the layout geometry of an LDMOS transistor includes curved regions such as when the transistor is shaped in a race-track or in loops, the LDMOS transistor can suffer from a low breakdown voltage at the curved regions due to electric field crowding effects. Electric field crowding effects describe the conditions where the surface electric field of an LDMOS transistor is higher at the curved regions of the transistor as compared to the parallel regions due to electric field crowding at the curved regions.
FIG. 2
illustrates a conventional race-track layout geometry of a LDMOS transistor. Because of electric field crowding effects, the breakdown voltages of the curved end regions (regions
20
and
22
) are lower than the breakdown voltages of the parallel or rectilinear regions. Thus, the breakdown voltage of the LDMOS transistor is limited by the breakdown voltage of the curved regions. A method for reducing the electric field crowding at the curved regions of an LDMOS transistor has been proposed where the buried layer in the LDMOS transistor is extended towards the drain of the transistor. (See, M. Amato, “Reduced Electric Field Crowding at the Fingertips of Lateral DMOS Transistors,” Proceedings of the Electrochemical Society, pp. 161-162, 1987.) While this method is effective in improving the breakdown voltage in the curved regions of an LDMOS transistor to match that of the parallel regions, the method also results in an overall increase in the on-resistance (R
on
) of the LDMOS transistor. A large increase in on-resistance of a transistor is undesirable, especially for high-voltage applications.
Therefore, it is desirable to optimize the breakdown voltage characteristics of an LDMOS transistor over the entire layout geometry of the transistor without severely impacting other device characteristics of the transistor.
SUMMARY OF THE INVENTION
According to the present invention, an LDMOS transistor incorporates one or more enhancement schemes for improving the breakdown voltage characteristics and ruggedness over the entire geometry of the transistor. In one embodiment, the LDMOS transistor is formed in an N-epitaxial layer with a polysilicon gate, N+ source and drain regions, p-type body region, and a field oxide region. The LDMOS transistor has a geometric shape including a rectilinear region and a curved region. The drain region is separated from the p-type body region by a first distance in the rectilinear region necessary to achieve a first breakdown voltage, and separated by a second distance in the curved region necessary to achieve at least the first breakdown voltage, where the second distance is greater than the first distance.
In another embodiment, the gate partially overlies the field oxide region by a third distance in the rectilinear region and by a fourth distance in the curved region, where the fourth distance is greater than the third distance.
In yet another embodiment, the LDMOS transistor incorporates both of the above embodiments such that the drain to body separation is extended in the curved region and the gate-over-field-oxide overlap is also extended in the curved region.
In other embodiments, the drain region of the LDMOS transistor can be formed in an N-well formed in the N-epitaxial layer.
The enhancement schemes optimize the breakdown voltage characteristics and ruggedness of the lateral DMOS transistor in both the rectilinear and curved regions.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
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patent: 4300150 (1981-11-01), Colak
patent: 4318216 (1982-03-01), Hsu
patent: 5473180 (1995-12-01), Ludikhuize
patent: 5517046 (1996-05-01), Hsing et al.
patent: 5633521 (1997-05-01), Koishikawa
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patent: 5846866 (1998-12-01), Huang et al.
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patent: 2277406 (1994-10-01), None
Amato, M., “Reduced Electric Field Crowding at the Fingertips of Lateral DMOS Transistors,” Abstract No. 312, pp. 161-162 (1987).
Yilmaz, Hamza, “Modeling and Optimization of Lateral High Voltage IC Devices to Minimize 3-D Effects, ”High Voltage and Smart Power Devices, pp. 290-294 (1987).
Fischer Phillip
Garnett Marty
Inn Bruce Lee
Tsuchiko Hideaki
Cook Carmen C.
Lee Eddie
Micrel Inc.
Nguyen Joseph
Patent Law Group LLP
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