LDD MOS transistor with improved uniformity and controllability

Details LDD MOS transistor with improved uniformity and controllability LDD MOS transistor with improved uniformity and controllability

1997-05-21

1998-05-05

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257374, 257408, 257900, H01L 27088

Patent

active

057478520

ABSTRACT:
A MOS integrated circuit device fabricated utilizing high energy, high current implanting of ions through a layer of oxide to form heavily doped source and drain regions which are self-aligned with a polysilicon gate. A thick portion of the oxide layer adjacent to the polysilicon gate prevents heavy doping in the substrate next to the gate. The oxide layer is removed and a lightly doped drain (LDD) implant forms an LDD region which is self-aligned with the gate. Using this method the source/drain and LDD implants are performed using only a single mask and etch operation, rather than two mask and etch operations which are necessary using a conventional process.

REFERENCES:
patent: 5132758 (1992-07-01), Minami
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5166096 (1992-11-01), Cote et al.
patent: 5200351 (1993-04-01), Hadjizadeh-Amni
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5324974 (1994-06-01), Liao
patent: 5426315 (1995-06-01), Pfiester
patent: 5472895 (1995-12-01), Park
"Submicrometer Salicide CMOS Devices With Self-Aligned Shallow/Deep Junctions," IEEE Electron Devices Letters, vol. 10, No. 11, 1 Nov., 1989, pp. 487-489.

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