LDD CMOS with wider oxide sidewall on PMOS than NMOS

Details LDD CMOS with wider oxide sidewall on PMOS than NMOS LDD CMOS with wider oxide sidewall on PMOS than NMOS

1991-03-28

1993-10-19

Larkins, William D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257408, 257900, H01L 27092

Patent

active

052548660

ABSTRACT:
A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors. Due to this structure, the widths of the side wall spacers (21, 22, 27, 28) as diffusion masks which are responsive to required characteristics, are attained for respective side walls of the gate electrodes (17, 18). The semiconductor device of such structure is manufactured by implanting impurity ions between the steps of forming the first and the second side wall spacers (21, 22, 27, 28) and each time covering prescribed region with a resist film (20, 23, 25, 29, 31, 33, 35).

REFERENCES:
patent: 4760033 (1988-07-01), Mueller
patent: 4935379 (1990-06-01), Toyoshima
patent: 4937645 (1990-06-01), Ootsuka et al.
patent: 5061975 (1991-10-01), Inuishi et al.

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