Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-11
2003-04-01
Mai, Son (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06543035
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for extracting the LCR (inductance, capacitance, and resistance) values of connecting line(s) in semiconductor integrated circuit (hereinafter LSI) design processes and to an LCR extraction program for causing a computer to execute that method, and particularly to a method and program capable of extracting highly precise LCR values of connecting line(s), taking into consideration the fluctuations in pattern width associated with the finer miniaturization of layout patterns.
2. Description of the Related Art
LSI design processes are ordinarily performed on computer CAD. An LSI design process has a logic design process for connecting logic gates to design a logic circuit, a layout design process for laying out that logic circuit on an actual chip, a process for extracting LCR (inductance, capacitance, and resistance) values of laid out connecting lines and determining the delay time for signal paths from the extracted LCR and the AC characteristics of cells and macros, a logic simulation process for checking whether the logic circuit will operate normally using that delay time, and a physical verification process for checking that the layout data satisfies the design rule.
Based on t he layout design, layout data, including wiring pattern data for each layer on the chip, are produced. Based on these layout data, the connecting line LCR values are extracted. The LCR extraction process, delay time computation process, and logic simulation process are generally provided in one program module.
In the LCR extraction process described above, the connecting line resistance R, capacitance C, and inductance L are extracted, either by arithmetic computation or by referencing a parameter table, according to the width of the wiring, the distances to adjacent wiring, and the overlapping area contained in the layout data.
In conjunction with the finer miniaturization of patterns in recent years and due to the influence of manufacturing processes, the actually formed pattern width sometimes differs from the pattern width in the layout data. One manufacturing process thought to affect the pattern width is the connecting line etching process. In processes such as reactive ion etching (RIE), wherein a reaction gas is introduced in a high vacuum atmosphere, a plasma state is induced by applying a high frequency voltage, and a wiring layer of aluminum or the like is etched, a phenomenon is observed whereby the pattern width fluctuates, becoming thinner or thicker, in conjunction with finer pattern miniaturization.
In conjunction with this pattern width fluctuation phenomenon, with a conventional method for extracting LCR values from the layout data, problems are encountered in that accurate LCR values cannot be extracted, the precision of the signal propagation delay time on signal paths determined by the extracted LCR values is low, and suitable logic simulation cannot be effected.
SUMMARY OF THE INVENTION
Thereupon, an object of the present invention is to provide both a new method wherewith it is possible to extract LCR values of connecting lines and the like, taking pattern width fluctuation into consideration, and a computer program for implementing that method.
Another object of the present invention is to provide both a method wherewith accurate LCR value extraction can be performed, even when the LSI design rule has been made even finer, and a computer program for implementing that method.
In order to attain the objects noted above, in one aspect of the present invention, an LCR extraction method for extracting LCR values containing at least one of resistance, capacitance, and inductance, from layout data at least having wiring pattern data in a plurality of wiring layers, has the steps of:
generating the LCR values, for a wiring pattern being looked at, based on the layout data for the wiring pattern being looked at;
finding the pattern congestion level in an area where the wiring pattern being looked at exists, based on the layout data; and
correcting the LCR values when the pattern congestion level is higher (more congested) than a prescribed reference value, based on pattern fluctuation values depending on the pattern interval between the wiring pattern being looked at and an adjacent pattern.
Pattern width fluctuations occur in manufacturing processes in conjunction with the finer miniaturization of layout data, wherefore the precision of extracted LCR values can be enhanced by subjecting the LCR values found from layout data to corrections corresponding to those pattern width fluctuations. Accordingly, signal path propagation delay times can be found more accurately using those corrected LCR values, and suitable logic simulations can be performed.
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Ohba Hisayoshi
Watanabe Jun
Fujitsu Limited
Mai Son
Staas & Halsey , LLP
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