Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-03
2006-10-03
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07117468
ABSTRACT:
Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit (“IC”) layout. For each particular net in a set of nets, the method specifies different spacing constraints for routing the particular net in different directions on the same layer. It then defines a particular route for each particular net in the set of nets, where the spacing between at least one particular route and an item adjacent to the route in the layout is different in the different directions on the same layer.
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U.S. Appl. No. 10/066,060, filed Jan. 31, 2002, Steven Teig, Per the preliminary amendment dated May 30, 2003, the present application is a CIP of this application.
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Jacques Etienne
Teig Steven
Cadence Design Systems Inc.
Dinh Paul
Stattler Johansen & Adeli LLP
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