Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-07-11
2004-08-31
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C430S005000
Reexamination Certificate
active
06785874
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout verification method of verifying layouts of semiconductor integrated circuits and a program thereof, as well as a layout verification apparatus.
2. Description of the Background Art
Recently, to comply with high integration and miniaturization of semiconductor integrated circuits, a rapid progress has been made in miniaturizing resist patterns formed on wafers and mask patterns for forming the resist patterns. In photolithography technique, in order to increase resolution as miniaturization is advanced, super resolution technique is being used as a method other than reducing the wavelength of a light source. As the super resolution technique, there are techniques called “Levenson method” and “modified illumination method,” respectively.
These methods comply with the miniaturization as follows. In Levenson method, a phase shifter is disposed on a mask to increase the resolution of a resist pattern to be formed on a wafer. In the modified illumination method, the shape of a light source itself is changed to increase the resolution of a resist pattern to be formed on a wafer. The use of these super resolution techniques permit a further miniaturized resist pattern, however, there might occur a dimensional variation different from that in conventional ones.
Specifically, in the method using no super resolution technique, it is arranged to prohibit layouts below resolution limitations of the line width of a wiring pattern and the space width (spacing width between lines). This provides a mask pattern layout on which the line width and the space width are both above the resolution limitations. As a result, there occurs no large dimensional variation between the mask pattern and a pattern to be formed on a resist (i.e., the finished pattern), and the dimensional variation of the finished pattern falls within a predictable range.
On the other hand, when using the super resolution technique, the resolution limitations of the line width and space width can be made small. However, in a certain dimensional range, the finished pattern dimension is far larger or smaller than a mask pattern. In some cases, the finished pattern dimension exceeds a permissible limit. It is also difficult to predict this.
Referring to
FIG. 16
, as is usual in manufacturing semiconductor devices, a circuit design and operation verification of the designed circuit are performed (step S
101
), followed by a layout design of a mask pattern for forming the circuit on a wafer (step S
102
). Subsequently, it is verified whether the layout thus obtained is proper or not (step S
103
), followed by a wafer making process (step S
104
).
In performing the layout design, it is required not be in contravention of (i.e., be free from errors in) a design rule (referred to as “DR” in some cases) R
1
that is determined based on restrictions of a process to be used. Hereat, the design rule is used in the layout design and layout verification in steps S
102
, S
103
, to specify the line width of wiring and the space width between wirings. Also, the design rule is to be limited by the wafer process.
In performing the layout verification, a design rule check (DRC) C
1
is performed to check, for example, whether the designed layout is in accordance with the design rule R
1
.
Thus, the technique comprising making a predetermined rule and verifying a layout based on the result of checking whether it is contravention of the rule, is called “rule base verification.” In the present circumstances where the above-mentioned super resolution technique is generally used, the design rule R
1
to be employed in the rule base verification is considerably complicated.
When using no super resolution technique in photolithography that is an exemplary wafer process, a design rule for the same layer is relatively simple. That is, the design rule is obtained only by specifying a minimum line width and a minimum space width, which indicate the limitation of the wafer process (e.g., the resolution limitation in photolithography technique).
On the other hand, when using the super resolution technique in a wafer process, a complicate design rule is required to comply with this technique. For instance, when forming a plurality of wiring patterns paralleling and having plural types of space widths, mere specifying of a minimum line width and a minimum space width is insufficient. It is therefore required to judge whether resolution is possible in a combination of a line width and a space width, that is, whether the finished pattern dimension exceeds a permissible limit.
Further, situations arise where no rule can be made, and the incidence of errors might be overlooked. Since the rule specifies the degree to which a pattern deviates, versatility is poor, thus making it difficult to comply with every pattern.
To overcome this problem, recently employed is a technique using optical simulation, which is called “model base verification.”
The optical simulation is technique of predicting the shape of a finished pattern of layout. Therefore, in the model base verification, a design rule complying with the super resolution technique can be made based on the predicted finished pattern shape. The actual simulation enables to understand exactly every layout pattern and its surrounding situations. Although the degree to which the pattern formation deviates depends on the simulation accuracy, this is recognizable with considerably more accuracy than the rule base verification.
However, the model base verification suffers from the drawback that, due to optical simulation, quite a long time is needed in predicting a finished pattern shape, thereby making it difficult to perform sufficient process evaluation such as the degrees of a defocus margin and an exposure margin.
Upon this, a technique of combining the model base verification and the rule base verification has been proposed. In this technique, optical simulation of the finished pattern of each layout is not performed design by design. In advance, the components of a pattern are subjected to optical simulation under a certain standardized conditions. Then, the design rule obtained by the simulation is applied to verification, thereby increasing verification accuracy and also reducing the time required therefor. Process evaluation can be performed with ease by associating the amounts of a defocus margin, an exposure margin or the like with the rule of components forming each pattern, although this makes the design rule complicated.
FIGS. 17 and 18
are diagrams illustrating an exemplary method of process evaluation in the verification technique mentioned above. This method is, for example, described in Japanese Patent Application Laid-Open No. 2001-014376 (2001).
Referring now to
FIG. 17
, each wiring pattern such as of wirings and gate electrodes is expressed by graphic data called “polygon.”
FIG. 17
exemplifies four polygons P
11
, P
22
, P
33
and P
44
. Each polygon is made up of a plurality of sides that are called “segment.” For example, the polygon P
11
is made up four sides of the segments Seg
1
to Seg
4
.
In the process evaluation, there has been employed a method of making a matrix table, as shown in FIG.
18
. To complete the matrix table, optical simulation is performed segment by segment, to obtain its evaluation data.
FIG. 18
shows a data table called “L (line)/S (space) matrix,” on which the ordinate and abscissa represent a plurality of numerical values of line widths and space widths of a wiring pattern, respectively, for convenience in understanding a plurality of combinations of line width and space width.
In
FIG. 18
, the ordinate indicates the numerical values of line widths (unit: &mgr;m), on which the numerical values from 0.14 &mgr;m to 0.4 &mgr;m are graduated in 0.02 &mgr;m, the numerical values from 0.4 &mgr;m to 1.2 &mgr;m are graduated in 0.1 &mgr;m, and the last value is not less than 1.5 &mgr;m. The abscissa indicates the numerical values of space widths, and they are likewise gra
Garbowski Leigh M.
Rossoshek Helen B
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