Layout verification method and method for designing...

Details Layout verification method and method for designing... Layout verification method and method for designing...

2007-02-06

2007-02-06

Pert, Evan (Department: 2826)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

11270594

ABSTRACT:
To provide a layout verification method capable of accurately detecting damage to be given to a gate, and to provide a higher-workability and higher-reliability design method to accurately detect damage to be given to a gate and to determine an approach for design correction to avoid damage, the layout verification method according to the invention is characterized in that an antenna value which is an estimated value of transistor gate damage is output based on an antenna ratio, and a fluctuation of plasma charging damage due to the layout near the transistor gate.

REFERENCES:
patent: 6496959 (2002-12-01), Noguchi
patent: 6550039 (2003-04-01), Noguchi
patent: 6862723 (2005-03-01), Wang et al.
patent: 2001/0010093 (2001-07-01), Nagayoshi et al.
patent: 11-214521 (1999-08-01), None
patent: 2001-210716 (2001-08-01), None

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