Layout structure of multi-use coupling capacitors in reducing gr

Details Layout structure of multi-use coupling capacitors in reducing gr Layout structure of multi-use coupling capacitors in reducing gr

1998-03-30

1999-12-07

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257379, 257390, 257532, 257773, H01L 2972

Patent

active

059988460

ABSTRACT:
A first mask includes a well mask formed over a first portion of the wafer to define a first conductive type well in the wafer. A first polysilicon mask is formed over the well mask including a plurality of first structures and a plurality of second structures to cover a first polysilicon layer, thereby defining polysilicon gates. A first implanting mask is formed over the first polysilicon mask for forming second conductive type region. A second implanting mask is formed over the first polysilicon mask for forming first conductive type region. A second polysilicon mask is formed between gates of a second conductive type MOS and gates of a first conductive type MOS. A contact hole mask is formed over the second polysilicon mask for forming contact holes. A metal mask is formed over the contact hole mask for forming connection.

REFERENCES:
patent: 5883423 (1999-05-01), Patwa et al.

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